Abstract: A method for allocating perishable products based on machine learning, includes using a sales estimation model to evaluate estimated sales of a plurality of perishable products in a predetermined period, using a rating model to calculate a predetermined rate of the plurality of perishable products in the predetermined period according to the estimated sales, using an allocation model to adjust an allocation ratio of the plurality of perishable products in a plurality of marketing channels according to the estimated sales and the predetermined rate if a current rate is lower than the predetermined rate, and determining the numbers of perishable products allocated to the plurality of marketing channels according to the allocation ratio.

Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.

Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: A dynamic consent management platform and a personal information management method thereof are provided.

Abstract: An electrothermal module includes a first conductive layer, a second conductive layer, and a heat generating layer. The first conductive layer and the second conductive layer respectively include silver metal. The heat generating layer has a first portion, the first portion is disposed between the first conductive layer and the second conductive layer to form an electrothermal conversion portion of the electrothermal module, and the heat generating layer includes a conductive carbon material.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

Abstract: The disclosure provides a local stretch packaging structure, including a substrate, a flexible electronic element, a plurality of light-emitting display elements, and a packaging layer. The flexible electronic element is disposed on the substrate. These light-emitting display elements are disposed on the flexible electronic element. The packaging layer includes a packaging area and a non-packaging area. The packaging area covers the upper surface and sidewalls of these light-emitting display elements. The non-packaging area is directly covered the flexible electronic element that is not disposed with these light-emitting display elements.

Abstract: A rate adjustment method includes a rate estimation model generating a plurality of estimated rates according to a plurality of training data, a revenue estimation model generating an estimated revenue according to the plurality of estimated rates, updating the rate estimation model according to the estimated revenue to generate an updated rate estimation model, and inputting a plurality of current data into the updated rate estimation model to update the plurality of estimated rates.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device (WCD) may communicate, via a wireless link, with an audio device using a first configuration having first values for communication parameters. The WCD may transmit an indication to switch to a second configuration based at least in part on a configuration switch trigger, the configuration switch trigger being based at least in part on one or more of a link quality metric associated with the wireless link or a change of a use state of the WCD, and the second configuration having second values for the communication parameters associated with a reduction in voltage-induced interference in an audio output of the audio device. Numerous other aspects are described.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device (WCD) may communicate, during a time period, with a peripheral device via a wireless connection, the wireless connection using a first channel for communication. The WCD may monitor a second channel during a concurrency time of the wireless connection, the second channel using a channel availability check (CAC) to obtain resources for communicating, and transmitting an indication to switch to the second channel for communication. In some aspects, the WCD may communicate with low-latency requirements. Numerous other aspects are described.

Abstract: Methods for fabricating an integrated circuit (IC) device with a protection liner between doped semiconductor regions are provided. An example IC device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. The insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. The insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, a transistor comprises a source, a drain, and a pair of spacers between the source and the drain. In an embodiment, a semiconductor channel is between the source and the drain, where the semiconductor channel passes through the pair of spacers. In an embodiment, the semiconductor channel has a first thickness within the pair of spacers and a second thickness between the pair of spacers, where the second thickness is less than the first thickness. In an embodiment, the transistor further comprises a gate stack over the semiconductor channel between the pair of spacers.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.

Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.

Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.

Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.

Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.

Abstract: Techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. A directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. After the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. Accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.