Patents by Inventor Chu Lin

Chu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220146207
    Abstract: A vapor chamber device has a housing and multiple chambers. The housing includes two shells opposite to each other. The chambers are formed between the two shells. Each chamber contains a working fluid and has at least one diversion bump and a capillary structure. The diversion bump is formed on an inner surface of the second shell, and the capillary structure is mounted on the diversion bump. Since the chambers are independent from one another, when the vapor chamber device is vertically mounted to a heat source, the chambers at an upper portion of the vapor chamber device still contain the working fluid. The working fluid in the vapor chamber device may not all flow to a bottom of the vapor chamber device. Therefore, a contact area between the working fluid and the heat source is increased and heat dissipation efficiency is improved.
    Type: Application
    Filed: December 7, 2020
    Publication date: May 12, 2022
    Inventors: Pu-Ju LIN, Ying-Chu CHEN, Wei-Ci YE, Chi-Hai KUO, Cheng-Ta KO
  • Publication number: 20220148526
    Abstract: A display apparatus including a display panel and a display driver is provided. The display driver is coupled to the display panel. The display driver is configured to drive the display panel by at least one of a plurality of gray levels to display an image frame in a first state. The display driver is configured to drive the display panel by a predetermined gray level to display a standby frame in a second state. The display driver determines the predetermined gray level of the standby frame according to the gray levels of the image frame. In addition, a driving method of a display apparatus is also provided.
    Type: Application
    Filed: August 26, 2021
    Publication date: May 12, 2022
    Applicant: E Ink Holdings Inc.
    Inventors: Yi-Sheng Lin, Chen Chu Tsai, Chia-Chun Yeh
  • Publication number: 20220143114
    Abstract: The present invention provides an active substance of Lactic Acid Bacteria, a composition comprising thereof and its use for promoting longevity, especially for increasing Cisd2 gene expression, reducing mitochondrial damage and delaying aging conditions such as nerve degeneration and sarcopenia.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: GRAPE KING BIO LTD.
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shin-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG
  • Publication number: 20220141596
    Abstract: A MEMS device and a method for manufacturing a MEMS device are provided. The MEMS device includes an anchor, a diaphragm structure, and a sealing film. The diaphragm structure is disposed over the anchor and has an opening through the diaphragm structure. The sealing film covers at least a portion of the opening of the diaphragm structure.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: WEI-CHU LIN, YI-CHUAN TENG, JUNG-KUO TU
  • Publication number: 20220139773
    Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 5, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li WANG, Shuen-Shin LIANG, Yu-Yun PENG, Fang-Wei LEE, Chia-Hung CHU, Mrunal Abhijith KHADERBAD, Keng-Chu LIN
  • Publication number: 20220130755
    Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 28, 2022
    Inventors: SHUEN-SHIN LIANG, KEN-YU CHANG, HUNG-YI HUANG, CHIEN CHANG, CHI-HUNG CHUANG, KAI-YI CHU, CHUN-I TSAI, CHUN-HSIEN HUANG, CHIH-WEI CHANG, HSU-KAI CHANG, CHIA-HUNG CHU, KENG-CHU LIN, SUNG-LI WANG
  • Publication number: 20220123152
    Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Khaderbad Mrunal Abhijith, Keng-Chu LIN, Yu-Yun PENG
  • Publication number: 20220108919
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 7, 2022
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Patent number: 11296187
    Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
  • Patent number: 11282931
    Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Chia-Ming Pan, Su-Yu Yeh, Keng-Ying Liao, Chih-Wei Sung
  • Publication number: 20220082523
    Abstract: A gas sensor and a method for manufacturing the gas sensor are disclosed. The gas sensor includes a substrate, a heating member disposed on the substrate, a sensing layer covering the heating member, and two electrodes respectively electrically connected to the sensing layer. The sensing layer includes a doping element with an electronegativity greater than 2. The method for manufacturing the gas sensor includes a deposition process stacking a heating member, a sensing layer, and two electrodes on a substrate by deposition, and a doping process introducing a doping gas when depositing the sensing layer.
    Type: Application
    Filed: November 4, 2020
    Publication date: March 17, 2022
    Inventors: Ting-Chang Chang, Yi-Ting Tseng, Chun-Chu Lin, Wen-Chung Chen, Po-Hsun Chen, Shih-Kai Lin
  • Publication number: 20220069208
    Abstract: A resistive random access memory and an initialization method thereof are disclosed. The initialization method includes irradiating a memory device with an electromagnetic wave and manipulating a switching voltage to switch the memory device between a high resistance state and a low resistance state. The electromagnetic wave has a frequency of above 1016 Hertz. The resistive random access memory includes a plurality of memory devices and a switching circuit respectively electrically connected to the plurality of memory devices. Each of the plurality of memory devices has a resistance-changing layer and two electrode layers respectively located on an upper surface and a lower surface of the resistance-changing layer.
    Type: Application
    Filed: November 4, 2020
    Publication date: March 3, 2022
    Inventors: Ting-Chang Chang, Yi-Ting Tseng, Chun-Chu Lin, Wen-Chung Chen, Shih-Kai Lin, Po-Hsun Chen
  • Publication number: 20220059556
    Abstract: A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.
    Type: Application
    Filed: August 24, 2020
    Publication date: February 24, 2022
    Inventors: Chi-Chung JEN, Yu-Chu LIN, Y.C. KUO, Wen-Chih CHIANG, Keng-Ying LIAO, Huai-Jen TUNG
  • Patent number: 11257753
    Abstract: The present disclosure provides an interconnect structure, including a substrate having a conductive region adjacent to a gate region, a contact over the conductive region, a first interlayer dielectric layer (ILD) surrounding the contact, a via over the contact, a first densified dielectric layer surrounding the via, wherein the densified dielectric layer has a first density, and a second ILD layer over the first ILD layer and surrounding the via, wherein the second ILD layer has a second density, the first density is greater than a second density.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Khaderbad Mrunal Abhijith, Yu-Yun Peng, Fu-Ting Yen, Chen-Han Wang, Tsu-Hsiu Perng, Keng-Chu Lin
  • Patent number: 11257963
    Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Wen-Chih Chiang, Ming-Hong Su, Yung-Han Chen, Mei-Chen Su, Chia-Ming Pan
  • Publication number: 20220028993
    Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.
    Type: Application
    Filed: October 8, 2021
    Publication date: January 27, 2022
    Inventors: Yu-Chu Lin, Chia-Ming Pan, Chi-Chung Jen, Wen-Chih Chiang, Keng-Ying Liao, Huai-jen Tung
  • Publication number: 20220020644
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure.
    Type: Application
    Filed: January 7, 2021
    Publication date: January 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu LIN, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11227794
    Abstract: A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
  • Patent number: 11217524
    Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shuen-Shin Liang, Ken-Yu Chang, Hung-Yi Huang, Chien Chang, Chi-Hung Chuang, Kai-Yi Chu, Chun-I Tsai, Chun-Hsien Huang, Chih-Wei Chang, Hsu-Kai Chang, Chia-Hung Chu, Keng-Chu Lin, Sung-Li Wang
  • Publication number: 20210407856
    Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tetsuji Ueno, Ting-Ting Chen