Abstract: Fin trim plug structures with metal for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure is over a first end of the fin. A gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of a region of the fin. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction. The first isolation structure and the second isolation structure both include a dielectric material laterally surrounding an isolated metal structure.

Abstract: In one example in accordance with the present disclosure, a computing device is described. The computing device includes a housing and a light source to illuminate through a window in the housing. The computing device also includes a controller. The controller determines a usage level of a processor of the computing device. The controller also adjusts a characteristic of the light source based on a determined usage level of the processor.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

Abstract: An electronic package is provided, in which a mesh structure is disposed between a circuit structure and an electronic element to increase the shunt path of current. Therefore, when the electronic element is used as an electrode pad of a power contact, the current can be passed through a conductive sheet of the circuit structure via the mesh structure, such that the power loss can be reduced and the IR drop of the electronic element can meet the requirements.

Abstract: A substrate-type multi-layer polymer capacitor (MLPC), including a casing, a core, a first electroplated terminal and a second electroplated terminal. The core is arranged in an inner cavity of the casing. The casing is formed by joining two first packaging plates with two second packaging plates. The first and second electroplated terminals are formed by electroplating. The first electroplated terminal is configured to cover one end of the casing to form an anode electrically led out from the core, and the second electroplated terminal is configured to the other end of the casing to form a cathode electrically led out from the core. The first packaging plate includes a substrate, an electrode plate and two metal plates. The first and second electroplated terminals are integrally sealed with the casing.

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.

Abstract: Aspects relate to transmission control. In some examples, a first apparatus (e.g., a wireless communication device) may output a first packet for transmission to a second apparatus. Subsequently, the first apparatus may suspend a second packet from being output for transmission to the second apparatus. In some examples, the suspension of the second packet may be based on a first voltage level of a power source being less than or equal to a first threshold (e.g., due to the transmission of the first packet).

Abstract: A semiconductor device includes a semiconductor substrate, an isolation feature, gate lines, and a first gate structure. The isolation feature is over the semiconductor substrate and surrounding an active region of the semiconductor substrate. The gate lines extend across the active region of the semiconductor substrate. The first gate structure is over the isolation feature. The first gate structure comprises a first gate line, a second gate line, and a first bridge portion, the first and second gate lines are substantially parallel with the gate lines, and the first bridge portion connects the first gate line to the second gate line.

Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.

Abstract: Techniques and apparatus for determining intrinsic resistance and/or battery life of a coin cell battery based on the recovery time of the battery voltage after a significant current draw event. Once the intrinsic resistance and/or battery life is known, a device powered by the coin cell battery can take action to lengthen the battery's useful lifetime. One example technique of operating a device powered by a battery generally includes performing an operation with a relatively high current draw from the battery compared to other operations of the device, determining a recovery time of a voltage of the battery after the operation, and estimating a position of the battery in a lifetime of the battery based on the recovery time.

Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.

Abstract: A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: A memory device includes a semiconductor substrate, a first continuous floating gate structure, a dielectric layer, and a control gate electrode. The semiconductor substrate has a first active region. The first continuous floating gate structure is over the first active region of the semiconductor substrate, wherein the first continuous floating gate structure has first and second inner sidewalls facing each other. The dielectric layer has a first portion extending along the first inner sidewall of the first continuous floating gate structure and a second portion extending along the second inner sidewall of the first continuous floating gate structure. The control gate electrode is over the dielectric layer. The control gate electrode is in contact with the first and second portions of the dielectric layer.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.

Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor nanostructure and a second semiconductor nanostructure stacked over a substrate. The semiconductor device structure also includes a first epitaxial structure connecting the first semiconductor nanostructure and a second epitaxial structure connecting the second semiconductor nanostructure. The semiconductor device structure further includes a gate stack wrapped around the first semiconductor nanostructure and the second semiconductor nanostructure. In addition, the semiconductor device structure includes a conductive contact electrically connected to the epitaxial structures. The conductive contact has a portion extending towards the gate stack from terminals of the first epitaxial structure and the second epitaxial structures. The first epitaxial structure is wider than the portion of the conductive contact.

Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.