Abstract: The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

Abstract: A method includes forming a device region over a substrate; forming a first dielectric layer over the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along sidewalls and bottom surfaces of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region includes a homogeneous mixture of the first conductive material and the second conductive material.

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate, wherein the isolation structure includes a first dielectric layer in contact with the semiconductor substrate and a second dielectric layer over the first dielectric layer, wherein the first dielectric layer is between the second dielectric layer and the semiconductor substrate, the first dielectric layer comprises a bottom portion and a sidewall portion, and a thickness of the bottom portion is greater than a thickness of the sidewall portion, wherein the first dielectric layer and the second dielectric layer comprise different materials, and wherein the first dielectric layer comprises a nitride of a semiconductor material.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Abstract: The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

Abstract: A method, apparatus, and computer-readable medium are provided that improve power management for devices communicating via Bluetooth (BT) over Internet Protocol (BTOIP). The apparatus for wireless communication for a first device receives a first set of packets from a second device during a time period associated with a training phase for the first device. The apparatus determines an arrival time of a first packet of the first set of packets. The apparatus determines, based on the arrival time and a wakeup time interval, a wakeup time for the first device. The apparatus causes, based on the wakeup time for the first device and one or more attributes associated with the first set of packets, a shutdown of the first device.

Abstract: A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.

Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first nitride-containing layer on a side of a carrier substrate, first semiconductor devices thermally coupled to the first nitride-containing layer, a first interconnect structure physically and electrically coupled to first sides of the first semiconductor devices, and a first metal-containing dielectric layer bonding the first nitride-containing layer to the first interconnect structure. A thermal conductivity of the first nitride-containing layer is greater than a thermal conductivity of the first metal-containing dielectric layer.

Abstract: Provided is a method of forming a semiconductor structure including: bonding a device wafer onto a carrier wafer; forming a support structure between an edge of the device wafer and an edge of the carrier wafer, wherein the support structure surrounds a device layer of the device wafer along a closed path; removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Abstract: A semiconductor device includes a substrate, a plurality of active structures, a trench, a lower epitaxy, an upper epitaxy and a bottom barrier portion. The active structures are formed on the substrate and arranged in a first direction. The trench passes through adjacent two of the active structures in a second direction and has a bottom recess. The lower epitaxy is formed on a lower portion of the trench. The upper epitaxy is formed on an upper portion of the trench and separated from the lower epitaxy. The bottom barrier portion is formed on the bottom recess and separates the substrate and the lower epitaxy.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

Abstract: A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.

Abstract: In an embodiment, a method includes: forming a sacrificial spacer in a contact opening, the contact opening exposing a source/drain region; depositing a spacer layer on a sidewall of the sacrificial spacer and on a top surface of the source/drain region; forming a protective dielectric on the spacer layer and in the contact opening; removing the sacrificial spacer to form a recess adjacent the spacer layer; and forming a dielectric cap in an upper portion of the recess by redepositing a material of the protective dielectric and a material of the spacer layer in the upper portion of the recess, the dielectric cap sealing a lower portion of the recess to form a void.

Abstract: An electronic device with light-indicating function is provided. The electronic device includes a substrate, a first light source, a second light source, and a light guiding element. The substrate includes a first surface and a second surface, wherein the first surface is opposite to the second surface. The first light source is disposed on the first surface of the substrate, wherein the first light source faces the first direction, and the first light source provides a first light beam. The second light source is disposed on the first surface of the substrate, wherein the second light source faces the second direction, the second light source provides a second light beam, and the first direction is not parallel to the second direction. The light guiding element includes a first section and a second section.