Abstract: A binding and configuration method for a bus adapter and a channel, a mapping manager, and a connection system are provided. The binding and configuration method for the bus adapter and the channel includes: configuring a mapping table of a mapping manager; associating a logical channel with a corresponding hardware channel based on the mapping table; and connecting the logical channel to the corresponding hardware channel for data communication. A common architecture for the application program to access bus adapter resources is realized. The application programs using this architecture can arbitrarily configure the bus adapter model and the hardware channel that need to be connected, and the mapping relationship takes effect immediately after each configuration change without modifying the user's software, thus improving the efficiency of the application program development and reducing the possibility of errors.

Abstract: A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.

Abstract: A cleaning system of a vehicle oil circuit is provided, including a filter unit, an oil storage unit and a flushing unit. The filter unit includes a filter chamber, a first oil inlet tube and an oil outlet tube. The first oil inlet tube is communicated with a first opening of the vehicle oil circuit. The oil outlet tube is communicated with a second opening of the vehicle oil circuit. The oil storage unit includes a waste oil chamber and a second oil inlet tube communicated with a third opening of the vehicle oil circuit. The flushing unit includes a flushing chamber and a flushing tube. The flushing chamber receives a washing oil. The flushing tube is communicated respectively with the flushing chamber and a fourth opening of the vehicle oil circuit. The flushing tube guides the washing oil to enter the vehicle oil circuit.

Abstract: A cleaning system for a vehicle oil circuit is provided, including a heat exchange unit. The heat exchange unit includes an oil inlet channel, a first container, a second container and an oil outlet channel. The first container is located within the second container. The first container defines a first space communicated with the oil inlet channel and the oil outlet channel, and the first container and the second container define a second space therebetween and non-communicated with the first space. The oil inlet channel guides an oil from the vehicle oil circuit to the first space, and the oil outlet channel discharges the oil from the first space. The first space receives the oil, and the second space receives a detergent. When the oil is in the first space, a heat of the oil is transferred to the detergent through the first container.

Abstract: A binding and configuration method for a bus adapter and a channel, a mapping manager, and a connection system are provided. The binding and configuration method for the bus adapter and the channel includes: configuring a mapping table of a mapping manager; associating a logical channel with a corresponding hardware channel based on the mapping table; and connecting the logical channel to the corresponding hardware channel for data communication. A common architecture for the application program to access bus adapter resources is realized. The application programs using this architecture can arbitrarily configure the bus adapter model and the hardware channel that need to be connected, and the mapping relationship takes effect immediately after each configuration change without modifying the user's software, thus improving the efficiency of the application program development and reducing the possibility of errors.

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Abstract: A patterning process is performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness. The patterning process includes: performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature which produces an intermediate light exposure in a target area followed by processing that creates openings in the photoresist layer in accordance with the mask and thins the photoresist in the target area due to the intermediate light exposure in the target area leaving thinned photoresist in the target area; performing middle layer etching to form openings in the middle layer aligned with the openings in the photoresist layer, wherein the middle layer etching does not remove the middle layer in the target area due to protection provided by the thinned photoresist; and performing trim etching to trim the middle layer in the target area.

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

Abstract: A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.

Abstract: A method for a selective detection of L-tryptophan (L-Trp) using formaldehyde as a medium is disclosed. The method includes preparation of a copper sulfide nanosheets-chitosan/acidified functionalized multi-wall carbon nanotubes (CuS NS-CS/F-MWCNTs) composite material, preparation of a composite film-modified electrode CuS NS-CS/F-MWCNTs/GCE, and a detection of the L-Trp. Since oxidation peaks of L-Trp and L-tyrosine (L-Tyr) overlap and are difficult to separate, the present invention provides a method for a highly selective detection of L-Trp through the Pictet-Spengler reaction of formaldehyde (HCHO) with L-Trp, in which the oxidation peak potential of L-Trp is shifted to 0.82 V and the oxidation peak potential of L-Tyr is 0.63 V, thereby effectively avoiding the interference of L-Tyr. The CuS NS-CS/F-MWCNTs/GCE is applied to detect L-Trp in the formaldehyde medium without any interference from L-Tyr or other amino acids with 50-fold concentrations.

Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for surfacing and interacting with electronic meeting insights are presented. A meeting request that includes a plurality of invitees may be received. The meeting request may be associated with a plurality of related documents based on one or more attributes and a meeting insight related to the related documents may be surfaced. The meeting request may have a low acceptance in relation to a threshold and a corresponding insight may be surfaced to reschedule the meeting. A user may send a time modification suggestion to the meeting organizer and a rescheduling insight may be surfaced. Time and location information corresponding to invitees and the meeting time may be analyzed and reminders may be surfaced for each of the invitees in relation to a meeting location. Attendees may interact with location-based insights to have directions to a meeting surfaced.

Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

Abstract: The present invention provides a processor including a source generator, a request synchronization signal generator and an output circuit. The source generator is configured to generate image data of a frame. The request synchronization signal generator is configured to generate a request synchronization signal to an integrated circuit only after the source generator generates the image data of the frame completely, wherein the request synchronization signal is used to trigger the integrated circuit to send a synchronization signal to the processor. The output circuit is configured to send the image data of the frame to the integrated circuit only after receiving the synchronization signal generated from the integrated circuit in response to the request synchronization signal.

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Abstract: The invention discloses an interpenetrating biopolymers network (IPN) hydrogel loaded with herbal extracts, preparation and application thereof. The IPN hydrogel can increase the preservation time of herbal extracts and achieve a long-term release mechanism of herbal extracts. The interpenetrating biopolymers network (IPN) hydrogel makes itself have microporous and macroporous network structure and reinforced gel structure. The gel itself has good hydrophilicity and high biocompatibility. In addition, the present invention will be subsequently applied to the development of hydrogel patches and preparation methods, which are composed of bidirectional elastic non-woven fabrics, hydrogels containing extracts and a cover film layer, and solve the common the problem of allergies caused by patches.

Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.

Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for surfacing and interacting with electronic meeting insights are presented. A meeting request that includes a plurality of invitees may be received. The meeting request may be associated with a plurality of related documents based on one or more attributes and a meeting insight related to the related documents may be surfaced. The meeting request may have a low acceptance in relation to a threshold and a corresponding insight may be surfaced to reschedule the meeting. A user may send a time modification suggestion to the meeting organizer and a rescheduling insight may be surfaced. Time and location information corresponding to invitees and the meeting time may be analyzed and reminders may be surfaced for each of the invitees in relation to a meeting location. Attendees may interact with location-based insights to have directions to a meeting surfaced.

Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.