Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.

Abstract: A feeding system with numerically adjustable pneumatic cylinder speeds includes: a frame; an X-axis pneumatic cylinder; a Z-axis pneumatic cylinder; a feeding table connected to the pneumatic cylinders in order to be driven into motion in the X- and Z-axis directions; an X-axis detection module; a Z-axis detection module; a microcomputer; and a display screen electrically connected to the microcomputer. The microcomputer uses each detection module to determine the time interval between the instant at which the piston rod of the corresponding pneumatic cylinder passes the corresponding starting point and a subsequent instant at which the same piston rod passes the corresponding endpoint. The time intervals thus determined are defined as a duration of X-axis forward movement and a duration of Z-axis forward movement respectively. Both durations are displayed on the display screen.

Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.

Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.

Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

Abstract: A feeding system with numerically adjustable pneumatic cylinder speeds includes: a frame; an X-axis pneumatic cylinder; a Z-axis pneumatic cylinder; a feeding table connected to the pneumatic cylinders in order to be driven into motion in the X- and Z-axis directions; an X-axis detection module; a Z-axis detection module; a microcomputer; and a display screen electrically connected to the microcomputer. The microcomputer uses each detection module to determine the time interval between the instant at which the piston rod of the corresponding pneumatic cylinder passes the corresponding starting point and a subsequent instant at which the same piston rod passes the corresponding endpoint. The time intervals thus determined are defined as a duration of X-axis forward movement and a duration of Z-axis forward movement respectively. Both durations are displayed on the display screen.

Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.

Abstract: A processor for use in an electronic device capable of displaying, having capability of switching a refresh rate for refreshing a display panel. The processor can dynamically transition between different states/scenarios in response to different triggering events. The processor can include an image stream consumer, configured to receive an input image stream and outputting an output image stream; a refresh rate selection controller, configured to select a refresh rate from a plurality of refresh rates in response to a monitoring of a current state/scenario; and a display controller, configured to receive the output image stream from the image stream consumer and transmit image data in the output image stream to a driving device, and in response to the selection by the refresh rate selection controller, control the driving device to refresh a display panel with the selected refresh rate.

Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.

Abstract: A processor for use in an electronic device is provided. The electronic device is capable of displaying and the processor has capability of switching a refresh rate for refreshing a display panel of the display device. The processor comprises: a refresh rate selection controller and a display controller. The refresh rate selection controller is configured to dynamically select one from a plurality refresh rates. The display controller is configured to control a driving device to refresh the display panel with the selected refresh rate and determine whether to adjust a data transmission rate over an interface between the processor and the driving device according to the selected refresh rate.

Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.

Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.

Abstract: A device generates blended frames, with each blended frame composed of multiple image layers and each image layer composed of multiple regions. The device includes display hardware. The display hardware retrieves a given image layer in a current frame from a memory. Based on at least content hints generated at the display hardware for the given image layer in the current frame, the display hardware makes a determination of whether to skip access to the memory for retrieving each region of each image layer in a next frame that is immediately after the current frame, and accesses the memory for the next frame according to the determination.

Abstract: A method for forming a pattern on a substrate is described. The method includes providing a substrate, forming a photosensitive layer over the substrate, exposing the photosensitive layer to a first exposure energy through a first mask, exposing the photosensitive layer to a second exposure energy through a second mask, baking the photosensitive layer, and developing the exposed photosensitive layer. The photosensitive layer includes a polymer that turns soluble to a developer solution, at least one photo-acid generator (PAG), and at least one photo-base generator (PBG). A portion of the layer exposed to the second exposure energy overlaps with a portion exposed to the first exposure energy.

Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.

Abstract: A method includes processing a first silicon wafer using a first focus condition, the first silicon wafer comprising: a first test pattern and a second test pattern, the first test pattern and the second test pattern being different. The method further includes determining a first critical dimension for the first test pattern, determining a second critical dimension for the second test pattern, determining a delta focus value based on the first critical dimension and the second critical dimension, and processing a second silicon wafer with a second focus condition, the second focus condition based on the delta focus value.