Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip extending from a sync drain on a top surface of the sync transistor to a control source on a top surface of the control transistor. The conductive clip may also connect to substrate pads such as a leadframe pad for current input and output. In this manner, the conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip electrically coupling a sync drain of the sync transistor to a first leadframe pad of the package, wherein the first leadframe pad of the package is electrically coupled to a control source of the control transistor using a wirebond. The conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction. A sync source is electrically and mechanically coupled to a second leadframe pad providing a high current carrying capability, and high reliability. The resulting package has significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.

Abstract: Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

Abstract: A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a buck converter; a boost converter, a buck boost converter, a forward converter and a flyback converter. The drain, source and gate pads of the monolithic CSC chip are connected to a lead frame by solder or epoxy or by bumping attach and a conductive connector or wire bonds connect the switch terminal to lead frame.

Abstract: A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.

Abstract: A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode.

Abstract: A method for fabricating an IC package that includes depositing conductive adhesive bodies on the leads, and then adhering the electrodes of an IC device to the so disposed conductive adhesive bodies.

Abstract: A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode.

Abstract: A multi-chip module that includes a conductive element connecting at least two semiconductor devices, the conductive element including enhancements for improving the mechanical coupling between the conductive element and the molded housing of the MCM.

Abstract: A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die.

Abstract: A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a buck converter; a boost converter, a buck boost converter, a forward converter and a flyback converter. The drain, source and gate pads of the monolithic CSC chip are connected to a lead frame by solder or epoxy or by bumping attach and a conductive connector or wire bonds connect the switch terminal to lead frame.

Abstract: A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die.

Abstract: A semiconductor package that includes a compound component and a diode arranged in a cascode configuration to function as a rectifier.

Abstract: A multi-chip module that includes a conductive element connecting at least two semiconductor devices, the conductive element including enhancements for improving the mechanical coupling between the conductive element and the molded housing of the MCM.

Abstract: A semiconductor package including a bidirectional compound semiconductor component and two power semiconductor devices connected in a cascode configuration.

Abstract: The semiconductor portion of a circuit includes a plurality of flip chip devices which are arranged in a planar fashion in a common housing. The plurality of flip chip devices are connected to each other without wire bonding. The common housing includes a packaging structure, the packaging structure including a connective portion and at least one web portion, which aids in the thermal management of the heat emitted by the plurality of flip chip devices and which connects the flip chip devices to each other. Passive devices in the circuit may also be arranged in a planar fashion in the common housing.