Abstract: A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode.

Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Abstract: A method for fabricating an IC package that includes depositing conductive adhesive bodies on the leads, and then adhering the electrodes of an IC device to the so disposed conductive adhesive bodies.

Abstract: A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.

Abstract: A semiconductor package that includes a compound component and a diode arranged in a cascode configuration to function as a rectifier.

Abstract: A semiconductor package including a bidirectional compound semiconductor component and two power semiconductor devices connected in a cascode configuration.

Abstract: A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the top of the substrate and are connected to further vias which extend to respective ball contacts at the substrate bottom. In one embodiment, the bottom surfaces and electrodes of the die are insulated and their tops (and drain electrodes) are connected by a moldable conductive layer. In another embodiment the top surface of the substrate is covered by an insulation cap, which may be finned for improved thermal properties. The passives are upended to have their longest dimension perpendicular to the substrate surface and are between the fin valleys.

Abstract: The semiconductor portion of a circuit includes a plurality of flip chip devices which are arranged in a planar fashion in a common housing. The plurality of flip chip devices are connected to each other without wire bonding. The common housing includes a packaging structure, the packaging structure including a connective portion and at least one web portion, which aids in the thermal management of the heat emitted by the plurality of flip chip devices and which connects the flip chip devices to each other. Passive devices in the circuit may also be arranged in a planar fashion in the common housing.

Abstract: A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the top of the substrate and are connected to further vias which extend to respective ball contacts at the substrate bottom. In one embodiment, the bottom surfaces and electrodes of the die are insulated and their tops (and drain electrodes) are connected by a moldable conductive layer. In another embodiment the top surface of the substrate is covered by an insulation cap, which may be finned for improved thermal properties. The passives are upended to have their longest dimension perpendicular to the substrate surface and are between the fin valleys.

Abstract: A semiconductor device is disclosed containing a semiconductor die having a trimetal electrode soldered to a substrate by a Sn—Sb solder.

Abstract: A semiconductor device is disclosed containing a semiconductor die having a trimetal electrode soldered to a substrate by a Sn—Sb solder.

Abstract: A power semiconductor package, comprising: a power MOSFET die having a bottom surface with a bottom electrode disposed for contacting a conductor on a support board, and having a top surface with a top electrode; a bump strap which bridges over the power MOSFET die, having mounting portions disposed respectively on opposite sides of the power MOSFET die and disposed for mounting on the support board, and a central portion which engages and is conductively connected to the top electrode of the power MOSFET die. The bottom electrode comprises at least one of a drain electrode and a gate electrode, and the top electrode comprises a source electrode. The bump strap extends upward from the mounting portions to define a respective pair of upper portions of the bump strap which are disposed above the power MOSFET die, the central portion of the bump strap being disposed lower than the upper portions so as to be adjacent to the top electrode of the power MOSFET die.

Abstract: A method of manufacturing a semiconductor device including a substrate and a die supported thereon. The substrate has at least one electrical connection region on a first portion of a surface of the substrate. The die has a bottom surface portion supported by a second portion of the surface of the substrate. The die also includes a top surface portion comprising a metal layer and a number of semiconductor elements below the metal layer. The top and bottom surface portions of the die are separated by a die body portion which lies above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical connection region on the first portion of the surface of the substrate.

Abstract: A power semiconductor package, comprising: a power MOSFET die having a bottom surface with a bottom electrode disposed for contacting a conductor on a support board, and having a top surface with a top electrode; a bump strap which bridges over the power MOSFET die, having mounting portions disposed respectively on opposite sides of the power MOSFET die and disposed for mounting on the support board, and a central portion which engages and is conductively connected to the top electrode of the power MOSFET die. The bottom electrode comprises at least one of a drain electrode and a gate electrode, and the top electrode comprises a source electrode. The bump strap extends upward from the mounting portions to define a respective pair of upper portions of the bump strap which are disposed above the power MOSFET die, the central portion of the bump strap being disposed lower than the upper portions so as to be adjacent to the top electrode of the power MOSFET die.

Abstract: An SO-8 type package contains a control MOSFET die mounted on one lead frame section and a synchronous MOSFET and Schottky diode die is mounted on a second lead frame pad section. The die are interconnected through the lead frame pads and wire bonds to define a buck converter circuit and the die and lead frame pads are overmolded with a common insulation housing.

Abstract: A semiconductor device including a substrate and a die supported thereon. The substrate has at least one electrical connection region on a first portion of a surface of the substrate. The die has a bottom surface portion supported by a second portion of the surface of the substrate. The die also includes a top surface portion comprising a metal layer and a number of semiconductor elements below the metal layer. The top and bottom surface portions of the die are separated by a die body portion which lies above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical connection region on the first portion of the surface of the substrate.

Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Abstract: A semiconductor device including a substrate and a die supported thereon. The substrate has at least one electrical connection region on a first portion of a surface of the substrate. The die has a bottom surface portion supported by a second portion of the surface of the substrate. The die also includes a top surface portion comprising a metal layer and a number of semiconductor elements below the metal layer. The top and bottom surface portions of the die are separated by a die body portion which lies above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical connection region on the first portion of the surface of the substrate.

Abstract: A semiconductor device includes: at least first, second, and third semiconductor dice, each having opposing surfaces which contain respective electrodes; a conductive lead frame including first and second separate die pad areas, the first and second semiconductor dice being disposed on the first die pad, and the third semiconductor die being disposed on the second die pad; a first plurality of pins being integral with and extending from one edge of the first die pad; a second plurality of pins being integral with and extending from one edge of the second die pad; a third plurality of pins being separated from one another and from the first and second die pads; a first plurality of bonding wires connecting one surface of the first semiconductor die to at least one of the third plurality of pins; a second plurality of bonding wires connecting one surface of the third semiconductor die to at least another one of the third plurality of pins; and a housing for encapsulating the lead frame, semiconductor dice, and

Abstract: A solderable back contact for semiconductor die consists of a titanium layer bonded to the bottom of the die. The free surface of the titanium layer is coated with a copper layer. A soft solder layer joins the bottom of the die to a copper lead frame by first heating the die to below the melting point of the solder, and then ultrasonically “scrubbing” the solder to cause it to bond to the die and lead frame with a minimum sized solder fillet.