Abstract: A method of forming a semiconductor device includes the following steps. A 2D material layer is formed over a bottom metal layer. A top metal layer is formed over the 2D material layer. An oxidation treatment is performed to the 2D material layer to form an oxide region interfacing both the 2D material layer and the top metal layer.

Abstract: A level shifter is disclosed. The input circuit receives an input signal operating within a first voltage range that is defined by a first voltage level. A pull-up circuit is coupled between a second voltage line and the input circuit. The second voltage line supplies a second voltage level. The second voltage level is higher than the first voltage level. A first connection node between the pull-up circuit and the input circuit serves as an output terminal of the level shifter. An acceleration circuit coupled to the first connection node accelerates the low-to-high transition at the output terminal. The acceleration controller for the acceleration circuit includes a first series of pulse generation transistors driven by first driving signals which have time differences therebetween, so that the acceleration controller enables the acceleration circuit in a pulse manner. The first driving signals are derived from the input signal.

Abstract: A coater cup deformation testing device includes a supporting board, a first plate and a second plate. The first plate is located on a first side surface of the supporting board. The first plate is circular and has a first diameter. The second plate is located on the first plate or on a second side surface of the supporting board. The second side surface is opposite to the first side surface. The second plate is circular and has a second diameter less than the first diameter. An area of each of the first and second plates is less than an area of the supporting board. A projection of each of the first and second plates on the supporting board is formed within the supporting board.

Abstract: The present invention provides, a novel method for producing a compound represented by formula (I) and a novel method for producing a compound represented by formula (B) or a salt thereof, which are intermediates in the production of formula (I).

Abstract: A microneedle device includes a substrate and a plurality of microneedle structures. The substrate is provided with a first surface, where the first surface has a surface roughness ranged from 0.05 ?m to 2.0 ?m. The plurality of microneedle structures are configured on the first surface. Because the surface of the microneedle device has a surface roughness of 0.05 ?m to 2.0 ?m, a film can be formed completely.

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

Abstract: A system including memory devices and a tester is provided. The tester is configured to: generate a first multi-purpose command to the memory devices and a first data signal to each of a first group in the memory devices to store a first identity; generate a second multi-purpose command to the memory devices and the first data signal to each of a second group in the memory devices to store a second identity; generate a third multi-purpose command and a fourth multi-purpose command to the memory devices to select the first and second groups in the memory devices to have first and second time shifts in write leveling pulses therein separately; transmit a write datum to the memory devices for performing a write operation to the memory devices; and receive read data and compare the write datum and the read data for a test result.

Abstract: Systems, devices, methods, and computer readable medium for evaluating visual quality of digital content are disclosed. Methods can include training machine learning models on images. A request is received to evaluate quality of an image included in a current version of a digital component generated by the computing device. The machine learning models are deployed on the image to generate a score for each quality characteristic of the image. A weight is assigned to each score to generate weighted scores. The weighted scores are combined to generate a combined score for the image. The combined score is compared to one or more thresholds to generate a quality of the image.

Abstract: A cutter module including a cutter plate and at least one knife unit is provided. The cutter plate includes a base and at least one positioning slot. The positioning slots are configured to distribute along the edge of the base. Each positioning slot is sandwiched between two adjacent side walls that protrude from the base. A positioning slot has a first spacing and a second spacing. The second spacing is closer to the edge than the first spacing, and the first spacing is larger than the second spacing. A knife unit is correspondingly disposed in a positioning slot. The knife unit has a first width and a second width and the first width is larger than the second width.

Abstract: A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.

Abstract: A protein system may include a mixer configured to combine a powdered protein mix with water to produce a liquid protein blend. A protein system may include a liquid protein batch tank fluidly coupled to the mixer and configured to receive the liquid protein blend from the mixer. A protein system may include a holding subsystem including a liquid protein holding tank fluidly coupled to the liquid protein batch tank and configured to store the liquid protein blend received from the liquid protein batch tank, wherein the liquid protein holding tank is configured to maintain a temperature of the liquid protein blend contained therein less than or equal to 40 degrees Fahrenheit.

Abstract: Neuroblastoma (NB) remains a leading cause of childhood cancer morbidity and mortality. Heritable activating mutations are present in the anaplastic lymphoma kinase (ALK) oncogene and these same mutations are frequently somatically acquired during high-risk NB tumorigenesis. ALK has been established as a tractable molecular target in NB and provides the rationale for the clinical development of ALK inhibition therapy. Anti-ALK antibodies and antigen binding fragments thereof are provided along with methods of use thereof.

Abstract: A power supply controller circuit for effectively saving power under an electrical specification is provided. First terminals of a capacitor and a third switch component are connected to a first terminal of a power supply device. First terminals of first and second switch components are connected to a second terminal of the capacitor. Second terminals of the first and second switch components are connected to a second terminal of the power supply device. A first terminal of a fourth switch component is connected to a second terminal of the third switch component. A control circuit controls operations of the first to third switch components and a driver circuit drives the fourth switch component in the power supply controller circuit, such that a current flowing through the power supply controller circuit to the second terminal of the power supply device is not smaller than a current threshold.

Abstract: A power-saving supply controller circuit of supplying power based on electrical specifications is provided. The power-saving supply controller circuit includes a first switch component, a second switch component and a control circuit. A first terminal of the first switch component and a first terminal of a capacitor are connected to a first terminal of a power supply device. Second terminals of the first and second switch components are connected to a second terminal of the power supply device. A first terminal of the second switch component is connected to a second terminal of the capacitor. When a current is supplied from the first terminal of the power supply device, the control circuit controls the first and second switch components such that a current flowing back to the second terminal of the power supply device is not smaller than a specified current.

Abstract: An insulated gate bipolar transistor is disclosed and includes a substrate, a collector, a gate, an isolation layer and a plurality of emitters. The substrate includes a trench and a drift area. The drift area is disposed corresponding to a first surface and includes a first conductive type. The trench is concaved from the first surface toward the drift area. The collector is formed on a second surface of the substrate and includes a second conductive type. The gate is formed in the trench. The isolation layer is formed between the gate and an inner wall of the trench, and includes side lines. The emitters are formed from the first surface of the substrate toward the drift area, are disposed adjacent to the side lines, and include the first conductive type. The emitters are arranged at intervals along the side lines, respectively.

Abstract: A method for embedding a data network graph includes: performing node feature extraction on a data network graph and a negative sample network graph using a first network embedding model, to obtain a positive sample embedding vector and a negative sample embedding vector performing node feature extraction on a first enhanced graph and a second enhanced graph of the data network graph using the first network embedding model, to obtain a first global embedding vector and a second global embedding vector; determining a first matching degree and a second matching degree; adjusting a parameter of the first network embedding model based on a loss value determined based on the first matching degree and the second matching degree; and performing node feature extraction on the data network graph based on an adjusted first network embedding model, to obtain an embedding vector configured for classifying each node in the data network graph.

Abstract: Disclosed herein is related to a method for extending lifespan and/or delaying aging in a subject; the method comprises administering to the subject with an effective amount of (24S)-3?-hydroxy-5?-stigmastan-6-one, wherein the delaying aging comprises increasing vitality, muscle strength or motor coordination, insulin sensitivity, or basal metabolic rate; and/or reducing muscle weakness, loss of balance, hair graying, kyphosis, or hyperglycemia. Also encompassed in the present disclosure are methods for promoting weight loss or treating type 2 diabetes mellitus in a subject, in which the methods comprise administering to the subject an effective amount of (24S)-3?-hydroxy-5?-stigmastan-6-one.

Abstract: A display device including a substrate, a cholesteric liquid crystal layer, and a transparent electrode layer that are sequentially stacked is provided. The cholesteric liquid crystal layer includes cholesteric liquid crystal molecules and a plurality of transparent photoresist structures. Each of the transparent photoresist structures is a closed structure, and the cholesteric liquid crystal molecules are respectively accommodated in a plurality of patterned areas respectively surrounded by the transparent photoresist structures, so as to form a plurality of cholesteric liquid crystal patterns. The transparent electrode layer includes a plurality of sub-electrodes. The cholesteric liquid crystal patterns are respectively driven by the sub-electrodes. An orthogonal projection of each of the transparent photoresist structures on the substrate falls in an orthogonal projection of a corresponding sub-electrode of the sub-electrodes on the substrate.