Abstract: An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body.

Abstract: A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

Abstract: A substrate structure is provided. A plurality of solder pads is positioned on a substrate. A solder mask covers the substrate and has a plurality of openings to respectively expose portions of the solder pads, wherein the openings have the shape of a polygon of at least five sides.

Abstract: The present invention discloses a staggered finger configuration comprising a plurality of first and second conducting wires alternately arranged on the substrate, wherein each of the first conducting wire connecting an inner and an outer fingers and each of the second conducting wire connecting an intermediate finger between the inner and the outer fingers, thereby forming a staggered configuration.

Abstract: A chip package including a carrier, a chip, a stiffener and a molding compound is provided. A producing method of the chip package includes the steps of disposing a bottom surface of the chip on the carrier; covering an edge of a top surface of the chip with the stiffener for protecting the edge; then wire bonding the top surface of the chip with the carrier; and forming the molding compound for encapsulating the chip, the stiffener and parts of the carrier.

Abstract: A system-in-package (SIP) device includes a substrate, a first chip and a chip package. The first chip is mounted and electrically connected to the substrate. The chip package is disposed above the first chip, and includes a leadframe, a second chip and a first encapsulant. The leadframe includes a die pad and a plurality of leads, wherein each lead is divided into an inner lead and an outer lead, and the outer lead is mounted and electrically connected to the substrate. The second chip is mounted on the die pad and electrically connected to the inner leads. The first encapsulant seals the second chip and a part of the leadframe, and exposes out the outer leads. The SIP device further includes a second encapsulant seals a part of the chip package, the first chip and the upper surface of the substrate, and exposes out the lower surface of the substrate.

Abstract: A circuit substrate includes a base and a plurality of conductive traces. The conductive traces are disposed on the base and on the same layer. The conductive traces include at least one first conductive trace. Wherein, the base has a cut region. The end of the first conductive trace is connected to the end portion of the cut region. The included angle between the rim of the end portion of the cut region and the first conductive trace is 75° to 105°.

Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

Abstract: A chip package and a producing method thereof are provided. The producing method of the chip package includes following steps. First, a bottom surface of a chip is disposed on a carrier, and a top surface of the chip is wire-bonded to the carrier. Then, a first molding compound is formed on an edge of the top surface of the chip to protect the edge. Afterwards, a second molding compound is formed to encapsulate the chip, the first molding compound and part of the carrier.

Abstract: The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer.

Abstract: A chip package including a carrier, a chip, a stiffener and a molding compound is provided. A producing method of the chip package includes the steps of disposing a bottom surface of the chip on the carrier; covering an edge of a top surface of the chip with the stiffener for protecting the edge; then wire bonding the top surface of the chip with the carrier; and forming the molding compound for encapsulating the chip, the stiffener and parts of the carrier.

Abstract: The present invention discloses a staggered finger configuration comprising a plurality of first and second conducting wires alternately arranged on the substrate, wherein each of the first conducting wire connecting an inner and an outer fingers and each of the second conducting wire connecting an intermediate finger between the inner and the outer fingers, thereby forming a staggered configuration.

Abstract: A circuit substrate comprising a base and a plurality of conductive traces is provided. The conductive traces are disposed on the base and on the same layer. The conductive traces include at least one first conductive trace. Wherein, the base has a cut region. The end of the first conductive trace is connected to the end portion of the cut region. The included angle between the rim of the end portion of the cut region and the first conductive trace is 75° to 105°.

Abstract: A process for manufacturing a substrate with an embedded capacitor is disclosed. A first metal wiring layer including a lower electrode pad is formed on a substrate base. A dielectric layer is formed a on the substrate base by build-up coating. A hole is formed in the dielectric layer to expose the lower electrode pad, then a medium material is filled into the hole. The medium material is ground to have a ground surface coplanar to the dielectric layer. A second metal wiring layer including an upper electrode pad is formed on dielectric layer, the upper electrode pad covers the ground surface of the medium material and is parallel to the lower electrode pad so as to form an embedded capacitor.

Abstract: A substrate includes a dielectric structure, an interconnection structure and a solder mask. The interconnection structure interlaces inside the dielectric structure. The solder mask covers the dielectric structure. The material of the solder mask can be the same as that of the dielectric structure contacting the solder mask. The material of the solder mask can be epoxy resin or bismaleimide-triazine.

Abstract: A method for forming ball pads of a BGA substrate is disclosed. A substrate is provided with a plurality of pad terminals on its surface. A solder mask is formed on the surface and has a plurality of openings to expose the pad terminals. A metal layer for redefining ball pads is formed on the solder mask. An etching mask is formed on the metal layer, the etching mask has a plurality of covering portions which are aligned with the pad terminals and larger than the openings of the solder mask. The metal layer is etched to form a plurality of redefined ball pads under the etching mask. The redefined ball pads cover the pad terminals of the substrate and extend around the openings of the solder mask so that solder balls can be jointed with the redefined ball pads to avoid contacting the solder mask and the pad terminals by redefinition of bonding area of solder balls.

Abstract: The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer.

Abstract: A ball grid array package substrate includes a substrate body having a surface. A least a ball pad and a solder mask are formed on the surface of the substrate body. The solder mask has an opening corresponding to the ball pads to enable the ball pad to have an exposed surface out of the opening of the solder mask. A patterned reinforcing metal layer is formed on the exposed surface of ball pads along a sidewall of the opening of the solder mask so that the sidewall of the opening will not directly contact the solder balls. Solder balls can be reflowed on the ball pads and the patterned reinforcing metal layers to increase jointing area and improve the shear strength of the solder balls.

Abstract: A process for manufacturing a substrate with an embedded capacitor is disclosed. A first metal wiring layer including a lower electrode pad is formed on a substrate base. A dielectric layer is formed a on the substrate base by build-up coating. A hole is formed in the dielectric layer to expose the lower electrode pad, then a medium material is filled into the hole. The medium material is ground to have a ground surface coplanar to the dielectric layer. A second metal wiring layer including an upper electrode pad is formed on dielectric layer, the upper electrode pad covers the ground surface of the medium material and is parallel to the lower electrode pad so as to form an embedded capacitor.

Abstract: A cavity down ball grid array package having a heat spreader, a substrate, a die, a plurality of conductive wires, a capsulation and a plurality of solder balls. The substrate has a first surface and a second surface. The first surface of the substrate is attached to the heat spreader. The substrate has a through hole that passes through the substrate and exposes the heat spreader. The substrate and the heat spreader are electrically connected. The die has a plurality of bonding pads on the active surface. The back surface of the die is attached to the heat spreader inside the through hole. One end of each conductive wire is electrically connected to a bonding pad while the other end of the conductive wire is electrically connected to the substrate. The encapsulation fills the through hole and encloses the die and the conductive wires. The solder balls are attached to the second surface of the substrate.