Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

Abstract: A cavity down multi-chips module package mainly comprises a substrate, a heat spreader, a plurality of chips and a carrier. The heat spreader is attached on the substrate via an adhesive so as to define a cavity through the opening passing through the substrate, and the carrier for redistributing electrical signals is disposed in the opening so as to be mounted on the heat spreader through another adhesive. Moreover, a plurality of chips are attached on the carrier and electrically connected to the carrier through first electrically conductive wires. Besides, the carrier is electrically connected to the substrate through second electrically conductive wires. Accordingly, the electrical signals can be transmitted from the chips to the substrate through the carrier, the first wires, and the second wires so as to shorten the electrical paths and to upgrade the electrical performance of the package.

Abstract: A substrate includes a dielectric structure, an interconnection structure and a solder mask. The interconnection structure interlaces inside the dielectric structure. The solder mask covers the dielectric structure. The material of the solder mask can be the same as that of the dielectric structure contacting the solder mask. The material of the solder mask can be epoxy resin or bismaleimide-triazine.

Abstract: A semiconductor build-up package includes a die, a metal carrier, and a plurality of dielectric layers. The metal carrier has a surface with a cavity for supporting the die. The surface of metal carrier is coplanar to the active surface of die for building up a plurality of dielectric layers. Each dielectric layer has metal columns for inner electrical connection. The metal carrier covers passive surface and sides of the die with a larger area for heat dissipating, so the heat generated from the die is dissipated fast through the metal carrier.

Abstract: A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.

Abstract: A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.

Abstract: A cavity down ball grid array package having a heat spreader, a substrate, a die, a plurality of conductive wires, a capsulation and a plurality of solder balls. The substrate has a first surface and a second surface. The first surface of the substrate is attached to the heat spreader. The substrate has a through hole that passes through the substrate and exposes the heat spreader. The substrate and the heat spreader are electrically connected. The die has a plurality of bonding pads on the active surface. The back surface of the die is attached to the heat spreader inside the through hole. One end of each conductive wire is electrically connected to a bonding pad while the other end of the conductive wire is electrically connected to the substrate. The encapsulation fills the through hole and encloses the die and the conductive wires. The solder balls are attached to the second surface of the substrate.

Abstract: A semiconductor build-up package includes a die, a circuit board and at least a dielectric layer. The circuit board has a surface for building up the dielectric layer, and the surface has a cavity for accommodating the die. The inside of multi-layer circuit board has conductive traces for expanding the electrical function of semiconductor build-up package. Each dielectric layer has conductive columns so that the die may electrically connect with the outermost dielectric layer. At least a conductive column is bonded on the surface of the multi-layer circuit board for inner electrical connection.

Abstract: A semiconductor build-up package includes a die, a circuit board and at least a dielectric layer. The circuit board has a surface for building up the dielectric layer, and the surface has a cavity for accommodating the die. The inside of multi-layer circuit board has conductive traces for expanding the electrical function of semiconductor build-up package. Each dielectric layer has conductive columns so that the die may electrically connect with the outermost dielectric layer. At least a conductive column is bonded on the surface of the multi-layer circuit board for inner electrical connection.

Abstract: A semiconductor build-up package includes a die, a metal carrier, and a plurality of dielectric layers. The metal carrier has a surface with a cavity for supporting the die. The surface of metal carrier is coplanar to the active surface of die for building up a plurality of dielectric layers. Each dielectric layer has metal columns for inner electrical connection. The metal carrier covers passive surface and sides of the die with a larger area for heat dissipating, so the heat generated from the die is dissipated fast through the metal carrier.

Abstract: A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.

Abstract: A substrate strip includes a plurality of substrate units wherein each of the substrate units is accepted for packaging a semiconductor package. The substrate strip comprises: a frame having at least one opening; at least one first substrate unit integrally formed with the strip frame; and at least one second substrate unit disposed in the opening and securely attached to the strip frame by an adhesive. The present invention further provides a method for making the substrate strip. The method is conducted by separating defected substrate units from a substrate strip and securely attaching accepted substrate units back to the substrate strip.

Abstract: A thermal enhanced ball grid array package is provided. The substrate for the package includes a metal core layer and at least a first patterned wiring layer provided thereon. A first insulating layer is provided between the first patterned wiring layer and the metal core layer. At least a second patterned wiring layer is provided on the substrate, opposite to the surface having the first patterned wiring layer. A second insulating layer having solder balls between the second patterned wiring layer and the metal core layer. The second patterned wiring layer is electrically connected to the first patterned wiring layer. Blind vias are provided in the second patterned wiring layer and the second insulating layer. A heat conductive material or solder material is filled into the blind vias to form thermal balls. The heat from the chip to the metal core layer is transferred directly through the thermal balls.

Abstract: A communication node is configured to automatically select an optimum common operational mode between itself and a link partner. The communication node sends advertisement packets across a fiber optic medium in order to broadcast its operational capabilities to the link partner. These operational capabilities may include 10BASE-FL and 100BASE-FL. Transitions may be inserted between the advertisement packets which may include clock pulses, data pulses and transitions. The communication node may be attached to a network having a bus architecture and may further be configured to identify an idle signal.

Abstract: A method of making a printed circuit board mainly comprises mechanically and electrically attaching a first substrate to a second substrate having an opening defined therein via solder balls, column-like solder bumps or anisotropic conductive adhesive film (ACF) thereby obtaining a multilayer circuit board with a cavity or a three-dimensional structure. The upper surface of the first substrate is provided with a first set of contacts adapted for electrical coupling to a semiconductor chip and a second set of contacts. For making electrical connection to an outside printed circuit board, the lower surface of the first substrate is provided with a third set of contacts which are designed to electrically interconnect to the first set of contacts and the second set of contacts. The second substrate is provided with a set of interconnection pads formed on a lower surface thereof.

Abstract: A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.

Abstract: A chip scale package comprises a film substrate attached to the active surface of a semiconductor chip by an adhesive layer. The adhesive layer has a plurality of apertures formed corresponding to bonding pads on the chip. The film substrate includes a film and a plurality of conductive leads formed thereon. The film has a plurality of first openings formed corresponding to the apertures of the adhesive layer and a plurality of second openings. Each lead on the film has a first end portion projecting into one of the first openings of the film and a second end portion exposed from one of the second openings of the film. Each aperture and corresponding first opening are filled with a conductive paste embedding the first end portion of one lead therein so as to electrically connect the bonding pads of the chip and the conductive leads of the film substrate. A plurality of solder bumps formed on the second end portions of leads through the second openings of the film.

Abstract: A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.

Abstract: A chip scale package comprises a film substrate attached to the active surface of a semiconductor chip by an adhesive layer. The adhesive layer has a plurality of apertures formed corresponding to bonding pads on the chip. The film substrate includes a film and a plurality of conductive leads formed thereon. The film has a plurality of first openings formed corresponding to the apertures of the adhesive layer and a plurality of second openings. Each lead on the film has a first end portion projecting into one of the first openings of the film and a second end portion exposed from one of the second openings of the film. Each aperture and corresponding first opening are filled with a conductive paste embedding the first end portion of one lead therein so as to electrically connect the bonding pads of the chip and the conductive leads of the film substrate. A plurality of solder bumps formed on the second end portions of leads through the second openings of the film.

Abstract: In a flip chip process, a wafer is provided with a plurality of chips therein. Each chip has an active surface on which are formed a plurality of bonding pads. A bump is formed on each bonding pad. A plurality of substrates respectively includes at least a package unit, wherein each package unit has a plurality of contact pads. The substrates are respectively mounted onto the wafer such that each package unit corresponds to one chip and the contact pads of the package unit are respectively connected to the corresponding bumps, wherein two neighboring substrates are separated by a gap. An underfill material fills between the wafer and the substrates, the underfill material being introduced through the gaps between the substrates and from the boundary of the wafer. The underfill material then is solidified. The substrates and the wafer are diced to form individualized packages.