Patents by Inventor Chuan Lin

Chuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365072
    Abstract: An electronic device is disclosed. The electronic device includes a display unit, a light sensor, and a processor. The display unit has a brightness value. The light sensor senses an ambient light to generate a light intensity signal. The processor is coupled to the display unit and the light sensor and accesses a program instruction from a memory to perform the following steps: continuously receiving the light intensity signal from the light sensor; smoothing a plurality of light intensity signals to generate a plurality of smoothing signals; and maintaining the brightness value of the display unit for a preset time period and then determining whether to adjust the brightness value when a difference generated by subtracting a previous smoothing signal of a target smoothing signal of the smoothing signals from the target smoothing signal is less than the first threshold or greater than the second threshold.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 19, 2020
    Inventors: Chih-Hsien YANG, Chih-Chuan LIN, Kou-Liang LIN, Chi-Liang TSAI, I-Hsi WU, Yu-Hao HU
  • Patent number: 10825914
    Abstract: A method of manufacturing a semiconductor device includes following steps. The substrate has a dummy region and a memory cell region. A plurality of first stack structures are formed over the substrate in the memory cell region. At least one second stack structure is formed over the substrate in the dummy region. A conductive layer is formed over the substrate to cover the first stack structures and the at least one second stack structure. A planarization process is performed on the conductive layer to expose top surfaces of the first stack structures and the at least one second stack structure. The conductive layer is patterned to form an erase gate between adjacent two first stack structures, and to form first and second select gates outside the adjacent two first stack structures.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chuan Lin, Chiang-Ming Chuang, Shang-Yen Wu
  • Publication number: 20200338874
    Abstract: A method of preparing an elastomer membrane with high water pressure resistance includes the following steps: preparing a dry material by subjecting first thermoplastic polyurethane (TPU) powder/particles to a drying treatment; preparing a first mixture by mixing the dry material thoroughly with one or a mixture of at least two of diethylenetriamine, diethylaminopropylamine, and diaminodiphenylmethane; preparing a second mixture by mixing an initiator thoroughly with the first mixture; preparing a first membrane layer from the second mixture; and preparing a second membrane layer and a third membrane layer through the above steps such that the second membrane layer and the third membrane layer are sequentially formed on the first membrane layer.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 29, 2020
    Inventors: Shu-Hui HUANG, Sheng-Jen LIN, Yao-Hung KUO, Jian-Fan CHEN, Hung-Kung CHIEN, Yu-chuan LIN, Yun-chin KUO
  • Publication number: 20200341676
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided.
    Type: Application
    Filed: May 29, 2019
    Publication date: October 29, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chieh Yang, Yi-Hsuan Lin, Tai-Yuan Huang, Ping-Chuan Lin
  • Publication number: 20200332079
    Abstract: A method of preparing a thermoplastic polyurethane membrane with high adhesion and high elasticity includes the following steps: (a) preparing a modifying solution, wherein the modifying solution is one or a mixture of at least two of diethylenetriamine, diethylaminopropylamine, and diaminodiphenylmethane; (b) preparing a semi-finished product by applying the modifying solution on at least one surface of a thermoplastic polyurethane membrane; and (c) subjecting the semi-finished product to a temperature of 50° C.˜180° C. in order for the semi-finished product to undergo a reaction and thus form the thermoplastic polyurethane membrane with high adhesion and high elasticity.
    Type: Application
    Filed: June 16, 2019
    Publication date: October 22, 2020
    Inventors: Shu-Hui HUANG, Sheng-Jen LIN, Yao-Hung KUO, Jian-Fan CHEN, Hung-Kung CHIEN, Yu-chuan LIN, Yun-chin KUO
  • Publication number: 20200326042
    Abstract: The specification and drawings present a new apparatus such as a lighting apparatus, the apparatus comprising at least one LED (or OLED) module, configured to generate a visible light such as white light, and at least one component such as optical component comprising a compound consisting essentially of the elements neodymium (Nd) and fluorine (F), and optionally including one or more other elements. The lighting apparatus is configured to provide a desired light spectrum by filtering the generated visible light using the compound. The at least one component can comprise a NdFxOy compound with values of x and y determining a content ratio F/O, which may be adjusted during manufacturing of the NdFxOy compound to provide desired output light parameters of the apparatus including at least a desired output light spectrum realized by filtering the generated visible light using the NdFxOy compound.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 15, 2020
    Applicant: Consumer Lighting (U.S.), LLC
    Inventors: Kevin Jeffrey BENNER, Thomas J. BOYLE, Dengke CAI, Thomas CLYNNE, William Erwin COHEN, Jean-Patrick DUCROUX, Jianmin HE, Jon Bennett JANSMA, Chuan LIN, Juliana P. REISMAN, Alok Mani SRIVASTAVA, Benjamin James WARD, Zhiyong WANG, William Robert WRIGHT, Qing YI
  • Patent number: 10763726
    Abstract: A wheel rim generator is provided, including: a wheel rim having a rim, a disc, and an axis of rotation; a bearing having an outer race and an inner race, said inner race is disposed around said rim within the rim width; a rotor configured to rotate with said outer race, has at least one permanent magnet, and a center of gravity being displaced from said axis of rotation; and a stator configured to rotate with said rim, form at least one magnetic circuit with said rotor, and generate electromotive force with one of constant and changing magnetic flux in said at least one magnetic circuit as said wheel rim rotates.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: September 1, 2020
    Inventor: Yi-Chuan Lin
  • Patent number: 10742360
    Abstract: Techniques and examples of layer mapping, channel state information (CSI) feedback and hybrid automatic repeat request (HARQ) feedback in mobile communications are described. A user equipment (UE) receives from a base station one or more reference signals, which may be non-zero power (NZP) or zero power (ZP), on one or more time-frequency resources indicated by a network via a communication link between the UE and the base station. The UE estimates, based on the receiving, a subspace spanned by a channel response of an interfering signal. The UE determines a precoding matrix indicator (PMI) based on the estimated subspace. The UE transmits to the base station a channel state information (CSI) feedback comprising at least the PMI. The PMI may include at least a first precoder and a second precoder.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: August 11, 2020
    Assignee: MediaTek Inc.
    Inventors: Weidong Yang, Lung-Sheng Tsai, Tzu-Han Chou, Yu-Chuan Lin, Bo-Si Chen
  • Patent number: 10720910
    Abstract: An eye diagram observation device is provided. The eye diagram observation device includes an eye diagram determination circuit and a clock generator. The eye diagram determination circuit obtains an eye diagram corresponding to an input signal pair based on a delayed sampling clock. The clock generator includes a voltage to time converter (VTC). The VTC generates a delayed clock based on a voltage value of an input voltage. The clock generator generates the delayed sampling clock based on the delayed clock. The eye diagram observation device may reduce power consumption and a layout area via the VTC.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 21, 2020
    Assignee: ASMedia Technology Inc.
    Inventor: Yu-Chuan Lin
  • Publication number: 20200210093
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: storing first data to a first physical erasing unit and marking the first physical erasing unit as belonging to a first group, wherein the first data belongs to a first type; storing second data to a second physical erasing unit and marking the second physical erasing unit as belonging to a second group, wherein the second data belongs to a second type which is different from the first type; selecting a third physical erasing unit as an active physical erasing unit and marking the third physical erasing unit as belonging to the first group; when a data moving operation is performed, moving valid data of the first physical erasing unit to the third physical erasing unit according to a first parameter of the first physical erasing unit.
    Type: Application
    Filed: February 18, 2019
    Publication date: July 2, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Ping-Chuan Lin, Shii-Yeu Chern, Tai-Yuan Huang, Yi-Hsuan Lin, Chi-Shun Kao
  • Patent number: 10696903
    Abstract: A reactor has an inner surface accessible to the hydrocarbon and comprising a sintered product of at least one of cerium oxide, zinc oxide, tin oxide, zirconium oxide, boehmite and silicon dioxide, and a perovskite material of formula: AaBbCcDdO3-?. 0<a<1.2, G?b?1.2, 0.9<a+b?1.2, O<c<1.2, 0?d?1.2, 0.9<c+d?1.2, ?0.5<?<0.5. A is selected from calcium, strontium, barium, and any combination thereof. B is selected from lithium, sodium, potassium, rubidium, and any combination thereof. C is selected from cerium, zirconium, antimony, praseodymium, titanium, chromium, manganese, ferrum, cobalt, nickel, gallium, tin, terbium and any combination thereof.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 30, 2020
    Assignee: General Electric Company
    Inventors: Yanfei Gu, Wenqing Peng, Shizhong Wang, Chuan Lin, Lawrence Bernard Kool, Zhaoping Wu, Qijia Fu, Zhigang Deng
  • Patent number: 10698261
    Abstract: A backlight module having a bearing plate and a light module is provided. The bearing plate has a bearing surface, which includes a trough, a first groove, a first inner stage, and a first outer stage. The first groove is disposed close to the trough. The first inner stage is between the trough and the first groove while the first outer stage is on the side of the first groove opposite to the first inner stage. The light module is disposed on the bearing surface and corresponds to the trough. Comparing to the first inner stage, the first outer stage is more protruding toward the light module.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 30, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Chung Huang, Yu-Chuan Lin
  • Publication number: 20200201452
    Abstract: An indicator device is suitable for a mixed reality device. The indicator device includes a body, a light source unit, at least two positioning elements, a triggering unit and a control unit. The light source unit is disposed on the body and generates a light source. The two elements are disposed separately on the body, wherein the light source unit and the positioning elements are disposed on different axes. The triggering unit is disposed on the body and generates a trigger signal. The control unit is disposed inside the body and is connected to the light source unit and the triggering unit. The control unit receives the trigger signal to generate a first control signal, thereby controlling the light-emitting state of the light source.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Shih-Bin LUO, Chun-Chuan LIN, Wen-Hung CHENG, Ming-Che WANG
  • Patent number: 10692855
    Abstract: An ESD protection device structure compatible with CMOS process is disclosed. In the ESD protection device structure, a power source I/O unit or a signal I/O unit of an I/O circuit is electrically connected to an electrostatic discharge clamp circuit including multiple low-voltage PMOS structure are formed in the P-type substrate and connected in series. Source and gate on low voltage N-type well of first low-voltage PMOS structure are electrically connected to a high-voltage power terminal pad through a first power line, or electrically connected to a signal transmission terminal pad through a signal transmission line, and drain of final low-voltage PMOS structure is electrically connected to a high voltage ground terminal pad through second power line. The ESD protection device structure using the serially-connected low-voltage PMOS structures only, can use the circuit layout area more efficiently and provide high ESD tolerance.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 23, 2020
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventors: Po-Chuan Lin, Shr-Hau Shiue
  • Patent number: 10685735
    Abstract: The invention provides a memory management method, a memory storage device, and a memory control circuit unit. The method includes: recording an error bit number of each upper physical programming unit and an error bit number of each lower physical programming unit of each of the physical erasing units; determining whether a first physical erasing unit is a bad physical erasing unit according to distributions of the error bit numbers of the upper physical programming units and the lower physical programming units of the first physical erasing unit of the physical erasing units; and performing a data transfer operation on data in the first physical erasing unit if the first physical erasing unit is determined as the bad physical erasing unit.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: June 16, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ping-Chuan Lin, Shii-Yeu Chern, Hsiang-Jui Huang, Ping-Yu Hsieh, Zih-Jia Wang, Yun-You Lin
  • Publication number: 20200183233
    Abstract: A backlight module having a bearing plate and a light module is provided. The bearing plate has a bearing surface, which includes a trough, a first groove, a first inner stage, and a first outer stage. The first groove is disposed close to the trough. The first inner stage is between the trough and the first groove while the first outer stage is on the side of the first groove opposite to the first inner stage. The light module is disposed on the bearing surface and corresponds to the trough. Comparing to the first inner stage, the first outer stage is more protruding toward the light module.
    Type: Application
    Filed: June 28, 2019
    Publication date: June 11, 2020
    Inventors: Chih-Chung Huang, Yu-Chuan Lin
  • Publication number: 20200165923
    Abstract: A gas turbine component includes a substrate and a corrosion resistant layer coupled to the substrate. The corrosion resistant layer includes zirconium silicate and is configured to protect the substrate from exposure to a vanadium corrodent.
    Type: Application
    Filed: April 25, 2017
    Publication date: May 28, 2020
    Inventors: Jianzhi ZHAO, Chuan LIN, Shizhong WANG, Mihir Kumar LAL, Richard Todd EVERHART
  • Publication number: 20200152583
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien MA, Haw-Chuan WU, Shih-Hao TSAI, Yu-Chuan LIN
  • Patent number: 10648940
    Abstract: An electrochemical biosensor includes a substrate, a plurality of layered active metal parts, a plurality of layered electrodes, a reaction confinement layer, an electrochemical reactive layer and a cover piece. The substrate is formed with through holes each of which is defined by an interior wall surface and penetrates top and bottom surfaces. Each of the layered active metal parts is formed at least upon a respective one of the interior wall surfaces. The layered electrodes are formed on the layered active metal parts. The reaction confinement layer confines a reactor space over a region where the through holes are formed. The electrochemical reactive layer is disposed in the reactor space and is electrically coupled to the layered electrodes.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: May 12, 2020
    Assignee: Taiwan Green Point Enterprises Co., Ltd.
    Inventors: Yu-Chuan Lin, Sung-Yi Yang, Yi-Cheng Lin
  • Publication number: 20200141560
    Abstract: An apparatus including at least one light emitting diode (LED) module, configured to generate visible light; and at least one component comprising a compound comprising elements of neodymium fluoride and a dopant to lower a refractive index of the compound as compared to neodymium fluoride, the compound configured with the LED module to provide a desired light spectrum by filtering the visible light generated by the LED module.
    Type: Application
    Filed: February 28, 2017
    Publication date: May 7, 2020
    Applicant: Consumer Lighting (U.S.), LLC
    Inventors: Qing YI, Jianmin HE, Chuan LIN, Zhiyong WANG, James Edward MURPHY, Dengke CAI, Xiaoyong WU