Patents by Inventor Chuan Lin

Chuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230077529
    Abstract: The invention provides a voltage doubler switched capacitor circuit capable of detecting short circuit of flying capacitor and a detection method thereof. The voltage doubler switched capacitor circuit provides a way to connect the flying capacitor in parallel to the charging path, and calculate whether it is charged to a predetermined voltage in the designed charging time interval, and then it can effectively detect whether the flying capacitor is short-circuited.
    Type: Application
    Filed: November 4, 2021
    Publication date: March 16, 2023
    Inventors: Po-Chuan LIN, I-Tsung LEE
  • Publication number: 20230078628
    Abstract: An isolated converter includes an input circuit, a transformer, a first switch, a second switch and a snubber circuit. The input circuit includes at least two input capacitors, and is configured to provide an input voltage. A divider node is arranged between the at least two input capacitors. The transformer includes a primary winding and a secondary winding to generate an output voltage on the secondary winding according to the input voltage. The primary winding of the transformer is electrically connected between the first switch and the second switch. The snubber circuit is electrically connected between the first switch and the second switch, and forms a discharge path with the primary winding. The snubber circuit is configured to receive a reflected voltage from the secondary winding back to the primary winding, and the divider node is connected to the discharge path.
    Type: Application
    Filed: July 29, 2022
    Publication date: March 16, 2023
    Inventors: Wen-Yu HUANG, Shih-Hsun WANG, Hung-Chuan LIN
  • Publication number: 20230056221
    Abstract: An electronic device includes an outer housing, a touch display module, and at least one optical assembly. The outer housing has an accommodating portion and an engaging portion. The touch display module is disposed in the accommodating portion and engaged with the engaging portion. The touch display module includes a thin-film transistor substrate, a color filter substrate, and a touch electrode layer. The color filter substrate is disposed on a side of the thin-film transistor substrate facing the outer housing. The touch electrode layer is disposed between the thin-film transistor substrate and the color filter substrate. The optical assembly is disposed on a side of the color filter substrate away from the thin-film transistor substrate.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 23, 2023
    Inventors: Ming-Chuan Lin, Sheh-Jung Lai, Kuo-Hsin Wang, Yu-Ling Chen
  • Patent number: 11586328
    Abstract: A circuit board includes multiple of first touch sensing electrodes, multiple of second touch sensing electrodes, and multiple of dummy patterns. The first touch sensing electrodes extend along a first direction. The second touch sensing electrodes extend along a second direction. The first touch sensing electrodes are electrically insulated from the second touch sensing electrodes. The first direction is not parallel to the second direction. The dummy patterns are positioned on the areas between the first touch sensing electrodes and the second touch sensing electrodes. The first touch sensing electrodes, the second touch sensing electrodes, and the dummy electrodes are non-transparent.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: February 21, 2023
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: Ming-Chuan Lin, Wen-Hung Wang, Chuan-Chih Fu
  • Patent number: 11587923
    Abstract: Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 21, 2023
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventor: Po-Chuan Lin
  • Publication number: 20230038878
    Abstract: A multispecific nanobodies chimeric antigen receptor and T-cell engager includes an HLA-G nanobody chimeric antigen receptor and a bispecific T-cell engager. The HLA-G nanobody chimeric antigen receptor includes an HLA-G nanobodies unit, a transmembrane domain, and a CD3z signaling domain. The bispecific T-cell engager includes a PD-L1 nanobodies unit and a CD3e nanobody.
    Type: Application
    Filed: July 20, 2022
    Publication date: February 9, 2023
    Inventors: Der-Yang CHO, Shao-Chih CHIU, Shi-Wei HUANG, Chih-Ming PAN, Chia-Ing JAN, Mei-Chih CHEN, Yu-Chuan LIN, Chung-Chun WU
  • Publication number: 20230030770
    Abstract: A driving circuit includes at least one light-emitting element, a drive line, a data line, a touch sensor, and a read line. The drive line is electrically coupled to a first terminal of the at least one light-emitting element. The data line is electrically coupled to a second terminal of the at least one light-emitting element. The drive line is electrically coupled to a first terminal of the touch sensor. The read line is electrically coupled to a second terminal of the touch sensor. The read line is electrically isolated from the data line.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 2, 2023
    Inventors: Ming-Chuan Lin, Wen-Hung Wang, Chuan-Chih Fu
  • Patent number: 11553863
    Abstract: A venous positioning projector includes an infrared light source module, a light splitting element, an infrared light image capture module, a processor, and a visible light projection module. The infrared light source module outputs a first infrared light to a target surface. The infrared light image capture module includes a filter and an infrared light image capture element. The light splitting element transmits a second infrared light reflected by the target surface to the filter. The infrared light image capture element receives the second infrared light passing through the filter. The processor generates venous image data according to the first infrared light and the second infrared light received by the infrared light image capture element. The visible light projection module generates a visible light based on the venous image data. The visible light is transmitted to the target surface through the light splitting element to generate a venous image.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: January 17, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Shih-Bin Luo, Chun-Chuan Lin, Wan-Ting Tien, Hua-Ying Sheng, Hsiao-Yue Tsao
  • Patent number: 11542644
    Abstract: A method of preparing polyester elastomer meltblown nonwoven fabric membrane with porous and high bonding strength includes the following steps of: (a) Adding a reaction solvent to a reaction solvent to thermoplastic polyester elastomer (TPEE) powder or granules to prepare a solvent mixture. (b) Adding a modifier to the solvent mixture, and mixing uniformly to prepare a first mixture, the modifier includes at least one of o-xylylenediamine, m-xylylenediamine, alpha, alpha?-diamino-p-xylene, 2,3,5,6-Tetrachloro-p-xylene-alpha,alpha?-diamine, and 1,3,5,7-Tetraazatricyclodecane. (c) Adding an initiator to the first mixture, and mixing uniformly to prepare a second mixture. (d) Drying the second mixture to form a masterbatch, and (e) preparing the polyester elastomer meltblown nonwoven fabric membrane by passing the masterbatch through a meltblown process.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN TEXTILE FEDERATION, R.O.C.
    Inventors: Shu-Hui Huang, Sheng-Jen Lin, Yao-Hung Kuo, Jian-Fan Chen, Yun-Chin Kuo, Yu-Chuan Lin
  • Patent number: 11520183
    Abstract: A touch front light module includes a touch light-guiding unit, a light-emitting unit, and a protective layer. The touch light-guiding unit includes a glass board, a touch layer disposed on a top surface of the glass board, and a microstructure layer disposed on a bottom surface of the glass board and which has a plurality of microstructures for light scattering. The light-emitting unit is disposed on a lateral side of the touch light-guiding unit and is configured to emit light to be incident on the lateral surface of the glass board. The protective layer is disposed on the touch layer. A touch display device including a display module and the touch front light module disposed on the display module is also disclosed.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: December 6, 2022
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: Sheh Jung Lai, Kuo Hsin Wang, Ming Chuan Lin, Yu Ling Chen
  • Patent number: 11520104
    Abstract: A robust conjugate symmetric optical apparatus is disclosed. The robust conjugate symmetric optical apparatus comprises a first optical cell set and a second optical cell set. The first optical cell set includes a first plurality of cells, each of which includes a first left half cell and a first right half cell, and the respective first right half cell and the corresponding first left half cells form a first symmetric structure therebetween.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: December 6, 2022
    Assignee: National Taiwan University
    Inventors: Wen-Jeng Hsueh, Yu-Chuan Lin, Shih-Han Chou
  • Patent number: 11500446
    Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.
    Type: Grant
    Filed: September 28, 2019
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Richard Fastow, Shankar Natarajan, Chang Wan Ha, Chee Law, Khaled Hasnat, Chuan Lin, Shafqat Ahmed
  • Publication number: 20220359324
    Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.
    Type: Application
    Filed: July 6, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Min-Han Chuang, Chia-Chu Lai
  • Publication number: 20220359374
    Abstract: An electronic module is provided, in which a first metal layer, an insulating layer and a second metal layer are sequentially formed on side faces and a non-active face of an electronic component to serve as a capacitor structure, where the capacitor structure is exposed from an active face of the electronic component so that by directly forming the capacitor structure on the electronic component, a distance between the capacitor structure and the electronic component is minimized, such that the effect of suppressing impedance can be optimized.
    Type: Application
    Filed: September 2, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Chia-Chu Lai, Min-Han Chuang
  • Publication number: 20220359975
    Abstract: An electronic package is provided, in which a ground layer is arranged on one side of an insulator, and a first antenna portion and a second antenna portion embedded in the insulator are vertically disposed on the ground layer, where a gap is formed between the first antenna portion and the second antenna portion, such that the first antenna portion and the second antenna portion are electrically matched with each other, and the ground layer is electrically connected to the second antenna portion but free from being electrically connected to the first antenna portion.
    Type: Application
    Filed: June 28, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Chu Lai, Ho-Chuan Lin, Min-Han Chuang
  • Patent number: 11495192
    Abstract: A display device includes a stacked structure and an outer frame fixedly receiving the stacked structure therein. The stacked structure includes an intelligence light adjustment layer, a display module, and a light-transmitting reflective layer interposed between the display module and the intelligence light adjustment layer. The intelligence light adjustment layer is configured to present one of a first state or a second state, which are different from each other, based on whether electrical power is applied to the intelligence light adjustment layer. The display module projects display images through the intelligence light adjustment layer in the first state. When the intelligence light adjustment layer is in the second state, the color of the outer frame is the same as the color of the intelligence light adjustment layer.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 8, 2022
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: Ming Chuan Lin, Chun Hui Tseng, Su Ming Lin
  • Patent number: 11484340
    Abstract: Disclosed is an arthroscopic cannula to solve the problem of more wounds being created due to the use of a plurality of cannulas in a conventional arthroscopic surgery. The arthroscopic cannula includes a cannula body, a spacer provided inside the cannula body and extending axially along the cannula body to divide an internal space of the cannula body into a first chamber and a second chamber, and a joint connected to one end of the cannula body. The interior of the joint intercommunicates with the first chamber and the second chamber.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 1, 2022
    Assignee: KAOHSIUNG MEDICAL UNIVERSITY
    Inventors: Pei-hsi Chou, Cheng-chang Lu, Yu-chuan Lin
  • Patent number: 11467758
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first write command from a host system; selecting a first physical erasing unit from at least one physical erasing unit available for writing and writing data corresponding to the first write command to the first physical erasing unit by using a single page programming mode or a multi-page programming mode when the number of physical erasing units available for writing is greater than a first threshold; and selecting a second physical erasing unit from the at least one physical erasing unit available for writing and writing data corresponding to the first write command into the second physical erasing unit by only using the single page programming mode when the number of physical erasing units available for writing is not greater than the first threshold.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: October 11, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chieh Yang, Yi-Hsuan Lin, Tai-Yuan Huang, Ping-Chuan Lin
  • Publication number: 20220320315
    Abstract: Provided is a method of manufacturing a semiconductor device including: providing a substrate having a memory cell region and a logic region; forming a plurality of stack structures on the substrate in the memory cell region; forming a polysilicon layer to cover the plurality of stack structures and the substrate in the logic region; performing a chemical-mechanical polishing (CMP) process on the polysilicon layer to expose top surfaces of the plurality of stack structures; and after performing the CMP process, patterning the polysilicon layer to form an erase gate between adjacent two stack structures and form a logic gate on the substrate in the logic region, wherein the logic gate has a topmost top surface lower than a topmost top surface of the erase gate.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 6, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chuan Lin, Chiang-Ming Chuang, Shang-Yen Wu
  • Publication number: 20220306742
    Abstract: The present disclosure provides an anti-T-cell nanobody that specifically binds to CD3 ?. The present disclosure also provides the nucleic acid sequence of the anti-T-cell nanobody, use of the anti-T-cell nanobody for treating cancer, immunoregulation and activating immune cells, and a method for detecting expression levels of CD3 ?.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 29, 2022
    Inventors: Der-Yang Cho, Shao-Chih Chiu, Shi-Wei Huang, Chih-Ming Pan, Mei-Chih Chen, Yu-Chuan Lin, Yeh Chen