Abstract: A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.

Abstract: A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Abstract: A method of controlling current includes receiving a current value detected by at least one regulator supplying a unit-specific voltage to each unit of an electronic device. The method also includes controlling a current flowing through the each unit on the basis of the current value.

Abstract: A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

Abstract: Provided are a battery charging method and an electronic device. The electronic device includes a connector that includes a first terminal to which a voltage is applied by an external charger and a second terminal for transmitting and receiving data, and a first charging circuit configured to charge a battery of the electronic device by using the voltage applied to the first terminal. The first charging circuit may include a communication circuit configured to transmit information related to the battery through the second terminal, a voltage converter configured to convert a voltage supplied to the battery and a first controller circuit configured to obtain first information regarding a voltage of the battery, control the communication circuit to transmit the first information to a charger connected with the connector, and control the voltage converter to charge the battery using a voltage adjusted based on the first information by the charger, if the adjusted voltage is applied to the first terminal.

Abstract: The present invention provides a locally invasive surgical apparatus including a manipulator for scratching the bone at a fracture site, a drive arm on which the manipulator is mounted, and a controller for controlling the manipulator and the drive arm. Therefore, it is possible to carry out minimally invasive surgery during bone fracture surgery, thereby enabling simple and quick bone fracture surgery for a speedy recovery.

Abstract: An electronic device is provided which includes a connector connected with an external electronic device, a plug connected with an external power source, a power supply circuit that supplies power to the external electronic device through the connector, a first charging module configured to receive first protocol-related charging request information and change a charging voltage and a charging current of the power supply circuit based on the charging request information, a second charging module configured to receive second protocol-related charging request information from the external electronic device, and a processor configured to convert the second protocol-related charging request information to the first protocol-related charging request information and transmit the converted first protocol-related charging request information to the first charging module.

Abstract: A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

Abstract: A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Abstract: A steel composition is provided and includes carbon of about 0.5 to 0.7 wt %; silicon of about 1.3 to 2.3 wt %; manganese of about 0.6 to 1.2%; chromium of about 0.6 to 1.2 wt %; molybdenum of about 0.1 to 0.5 wt %; nickel of about 0.05 to 0.8 wt %; vanadium of about 0.05 to 0.5 wt %; niobium of about 0.05 to 0.5 wt %; titanium of about 0.05 to 0.3 wt %; cobalt of about 0.01 to 3 wt %; zirconium of about 0.001 to 0.2 wt %; yttrium of about 0.01 to 1.5 wt %; copper of about 0.3% or less but greater than 0 wt %; aluminum of about 0.3% or less but greater than 0 wt %; nitrogen of about 0.03% or less but greater than 0 wt %; oxygen of about 0.003% or less but greater than 0 wt %. Additionally, a balance iron, based on the total weight is included.

Abstract: A fixing pin for orthopedic surgery is provided. The fixing pin for orthopedic surgery includes: an inner fixing pin inserted from one-side cortex of a bone to the opposite-side cortex thereof; an outer fixing pin including a first hole and a first screw portion formed to protrude from a front end thereof, the first hole being penetrated by the inner fixing pin so that front and rear ends of the inner fixing pin protrude, the outer fixing pin being inserted into only one-side cortex of the bone, and the inner fixing pin being fixed to the outer fixing pin; and a sleeve including a second hole and fixed to the outer fixing pin, the second hole being penetrated by the outer fixing pin so that front and rear ends of the outer fixing pin protrude. Therefore, according to the present disclosure, it is possible to perform internal fixation even after reposition of bone fracture has been performed using a fixing pin.

Abstract: A memory system is provided which includes multiple semiconductor memories having arrays of memory cells and a memory controller configured to provide an address in common to the multiple memories. First and second addresses corresponding to first and second rows of memory cells in first and second memories are selected according to the address in common. The first row and its adjacent rows in the first memory can all be different from the second row and its adjacent rows in the second semiconductor memory. Different conversion schemes can provide scramble information used to convert the address in common into the first and second addresses.

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Abstract: An electronic device including: a housing, a battery mounted within the housing, a power interface disposed to or within the housing and configured to receive power from an external power source wirelessly or through a wire, and a circuit configured to electrically connect the battery and the power interface. The circuit includes a first electrical path configured to supply a first part of a current supply from the power interface to the battery, and a second electrical path configured to supply a second part of the current supply from the power interface to the battery and connected to the battery in parallel to the first electrical path. The circuit is configured to selectively control the current supply to the battery via the second electrical path at least partially based on at least one of a charge level of the battery or a signal from a sensor disposed in the housing.

Abstract: A method and an apparatus for rapid charging in an electronic device are provided. In a method for charging a battery of an electronic device, an operation environment of the electronic device is determined. A charging current corresponding to the operation environment of the electronic device is set. Battery charging is started using the set charging current. The battery is charged using a maximum allowed charging current, such that a battery charging time may be reduced.

Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.

Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.

Abstract: At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing.

Abstract: An electronic device is provided. The electronic device includes a battery, a power management integrated circuit (PMIC), that is electrically connected to the battery, adjusts at least part of power received from the battery, and outputs a controlled power, a processor electrically connected to the PMIC, at least one power sensor that is one of electrically connected between the battery and the PMIC and constitutes a part of the PMIC, and a control circuit electrically connected to the at least one power sensor. The control circuit acquires at least one of a current value and a power value input into the PMIC from the battery, determines whether at least one of the acquired current value and power value is greater than or equal to a threshold, and generates a first signal for controlling at least one of the PMIC and the processor, at least partially based on the determination.