Abstract: A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device.

Abstract: The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.

Abstract: A driving device of a synchronous rectification apparatus is provided. The driving device includes a voltage detection part disposed on a power input terminal to detect a voltage value of a power inputted through the power input terminal, an adjustment part receiving the voltage value detected through the voltage detection part, the adjustment part adjusting the receive voltage value to output the adjusted voltage value, and a comparison part receiving the voltage value adjusted through the adjustment part into a positive terminal and a synchronous rectification starting value into a negative terminal, the comparison part outputting an command value of the synchronous rectification apparatus, which is obtained by comparing the received voltage value with the synchronous rectification starting value.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract: A charging control method and an electronic device for handling the method are provided. A power management device includes a power switch for providing a power path between a battery and a terminal set, and a control module configured to control the power switch to provide a charging function by forming the power path between the battery and the terminal set and provide a battery protection function by forming a discharging path or a charging path with respect to the battery.

Abstract: A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

Abstract: A method of performing a charging function by using different types of energy sources and an electronic device thereof are provided. The electronic device includes different types of circuits configured to acquire different types of energy sources, and a processor configured to determine an energy source for charging among the different types of energy sources based on respective current values for the different types of energy sources, and control the determined energy source for charging so as to be used in battery charging of the electronic device or in a system operation of the electronic device.

Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

Abstract: An inductor device is provided. The inductor device includes a coil unit that includes a pair of first and second coils disposed adjacent to each other and coupled to each other, a core unit that surrounds inner and outer spaces of the coil unit, and an induction unit that is disposed in the coil unit and is induced by a magnetic field generated between the first and second coils.

Abstract: A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.

Abstract: In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Abstract: A memory module may include m memory devices. Each of the m memory devices may be divided into n regions each region including a plurality of rows corresponding to row addresses, where m and n are integers equal to or greater than 2. An address detector included in each of the m memory devices, wherein for each of the address detectors, the address detector may be configured to count a number of accesses to a particular row address included in one region of each of the m memory devices during a predetermined time period, and be configured to output a detect signal when the number of the counted accesses reaches a reference value. Each of the max-count address generators may be configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses.

Abstract: A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.

Abstract: Provided is a profiling unit and method for profiling a number of times that an input/output address of a semiconductor device is accessed. The profiling unit includes a hash unit configured to produce at least one hash value by perform a hash operation on the input/output address, and a profiling circuit configured to profile the number of times that the input/output address is accessed by using the at least one hash value.

Abstract: The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract: A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

Abstract: The present invention provides a locally invasive surgical apparatus including a manipulator for scratching the bone at a fracture site, a drive arm on which the manipulator is mounted, and a controller for controlling the manipulator and the drive arm. Therefore, it is possible to carry out minimally invasive surgery during bone fracture surgery, thereby enabling simple and quick bone fracture surgery for a speedy recovery.