Abstract: Provided is an apparatus and method for canceling interference by a base station in a wireless mobile communication system. The method includes measuring a state of a channel with a mobile station, determining metric function values for channels that act as interference to the channel of the mobile station, selecting a predetermined number of interference channels in descending order of the metric function values, determining a weight vector for removing a signal transmitted over the interference channels, and applying the determined weight vector to a transmission signal and transmitting the weight vector applied signal.

Abstract: An apparatus and method for beamforming in a communication system are provided, in which a base station receives a channel vector from each of a plurality of mobile stations, generates an uplink channel matrix using the received channel vectors, generates a beamforming weight vector using the uplink channel matrix and a fixed constant that minimizes a channel error rate, and forms beams using the beamforming weight vector.

Abstract: Provided is an apparatus and method for determining a transmission mode for a base station in a wireless mobile communication system. The method includes measuring a state of a channel with a mobile station, determining whether channel states between the mobile station and a predetermined number of other mobile stations are orthogonal to each another, determining a space division multiple access (SDMA) mode as the transmission mode for the base station if the channel states are orthogonal to each other, and determining a beamforming (BF) mode as the transmission mode for the base station if the channel states are not orthogonal to each other.

Abstract: An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: A method and apparatus for resetting a memory card having a plurality of interfaces and a plurality of function blocks, wherein each function block may be associated with a corresponding interface, may include detecting a reset signal for a selected interface of the plurality of interfaces, and interrupting a function block associated with the selected interface. When the selected interface is the only active interface, all function blocks in the memory card may be reset. If interfaces other than the selected interface are active, only the selected interface may be reset.

Abstract: A system, apparatus and method are provided for discerning a host interface, the system including a host having at least one interface, a device in signal communication with the at least one interfaces an interface identifier for identifying a specification of the at least one interface, the interface identifier having at least one electrical characteristic sensor in signal communication with the at least one interface, at least two switches coupled to the at least one interface, each switch in signal communication with a corresponding pull resistor coupled to a pull voltage, and a selectable device interface in signal communication with the host for communicating with the host in response to the electrical characteristic sensor the apparatus including an interface identifier having at least two switches coupled to an interface, each switch in signal communication with a corresponding pull resistor coupled to a pull voltage; and the method including connecting at least one pull resistor to the interface, sequ

Abstract: A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substrate and forms a floating gate pattern on the insulating layer. The example method selectively implants ions in a portion of the insulating layer exposed by the floating gate pattern and forms a self-aligned element isolation film on the floating gate pattern by oxidizing and growing the portion of the insulating layer to which the ion implantation is performed.

Abstract: An integrated circuit card system and method are disclosed. The integrated circuit card system may include a host and a memory card for storing test data transferred from the host. The host may transfer the test data to the memory card when a processing time of the memory card exceeds a reference time. The memory card may calculate the test data transferred from the host, and the host may read out the calculated test data.

Abstract: An apparatus and method for allocating radio resources in a wireless communication system are provided, in which a channel variation detector detects channel variations of mobile stations (MSs) using channel information estimated from a sounding channel included in a received signal and a scheduler determines sounding channel allocation periods for the MSs and selects MSs to which the radio resources will be allocated according to the channel variations of the MSs.

Abstract: An example embodiment of the present invention relates to a method of executing a logic operation while remaining safe from side channel attacks. Another example embodiment of the present invention relates to a logic circuit and device for executing a logic operation while remaining safe from side channel attacks.

Abstract: The present invention relates to a method for adaptive menu design and items presentation reflecting cognitive characteristics. More particularly, the present invention relates to a technique to provide menu items reflecting human cognitive characteristics so as to apply for computer OS, the Internet browsers, and personal data assistants (PDAs) as well as computer programs.

Abstract: A system and method for controlling a plurality of home appliances provided in a building, wherein home appliance built-in communication modules are each adapted to convert information in an Ethernet standard format into that of a home appliance standard format and adapters are provided to connect the home appliance built-in communication modules to a phoneline network alliance (PNA) provided in the building to transmit and receive information therebetween. The home appliances can be controlled over a network using an existing telephone line. The adapters allow interconnection of the plurality of home appliances with no distance limitations.

Abstract: Provided is a method of fabricating a nonvolatile memory device. According to the method, in a semiconductor substrate where a cell region and a logic region are defined, an isolation region and an active region are defined in each of the cell region and the logic region, and a low voltage region and a high voltage region are defined in the logic region, a shallow trench isolation region is formed in the isolation region. A first gate insulating layer and a first gate electrode are formed in one region of the cell region. Second and third gate insulating layers are formed in respective regions of the logic region. A semiconductor layer is deposited on an entire surface of the semiconductor substrate. The semiconductor layer is etched to form a second gate electrode to overlap a portion of the first gate electrode. An entire surface of the semiconductor substrate is coated with a bottom antireflection coating layer.

Abstract: A microfluidic device for controlling the flow of a micro amount of fluid is provided. The microfluidic device is manufactured by binding a sensing substrate including a sensing electrode, an electrode interconnect, and a electrode pad, with a channel substrate including at least two fluid inlet ports, a chamber, and a channel, wherein a first fluid injected via one of the fluid inlet ports flows by natural capillary force, and a second fluid injected via another fluid inlet port is forced to flow by an external pump. The microfluidic device controls fluid flow and flow stoppage by a combination of natural capillary flow and an externally applied pressure as a result of the action of a pump.

Abstract: There are provided a NOR-type non-volatile memory having a split gate and a method of manufacturing the same. The split gate includes a block that protrudes above a semiconductor substrate, a first electrode formed on one side wall of the block, an inter electrode dielectric layer formed on the block and the first electrode, and a second electrode formed on the inter electrode dielectric layer and extended from the top of the block to the side wall of the first electrode. The first electrodes are formed on the side walls of the block in the form of spacers. The plurality of blocks and first electrodes are formed in the direction of a word line to form a cell array.

Abstract: A method for forming gate dielectric layers having different thicknesses is provided, The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and the upper oxide layer in a first region, while removing the nitride layer and the upper oxide layer in second, third, and fourth regions; forming the first gate dielectric layer having a first thickness in the second, third, and fourth regions; performing a second deglaze process to the first gate dielectric layer in the third region, thereby forming a second gate dielectric layer having a second thickness; and performing a third deglaze process on the first gate dielectric layer on the fourth region, thereby forming a third gate dielectric layer having a third thickness.

Abstract: The invention relates to yellow phosphor with a red wavelength region thereof reinforced and a white light emitting device incorporating the same. The yellow phosphor has a formula of Mx(Al, Ga)5O12:Cey,Euz, in which M is at least one selected from a group consisting of Tb, Y, Gd, La and Sm, where 2.4?x?2.998, 0.001?y?0.3 and 0.001?z?0.3.

Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.

Abstract: The present invention relates to phosphor blend for wavelength conversion and a white light emitting device using the same. The phosphor blend of the invention comprises three phosphors, A5 (PO4)3Cl:Eu2+, D2SiO4:Eu, and MS:Eu at a composition where near ultraviolet radiation is converted into light positioned at a CIE coordinate (x, y),where 0.25?x?0.45 and 0.25?x?0.43, wherein A comprises at least one of Sr, Ca, Ba, and Mg, D comprises at least one of Ba, Sr, and Ca, and M comprises at least one of Sr and Ca. Furthermore, the present invention provides a new white light emitting device in combination of the phosphor blend and a near ultraviolet LED.