Patents by Inventor Chul Yoon

Chul Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IMAGE PROCESSING DEVICE FOR COMPUTING AN INITIAL PHASE HAVING MAGNITUDE AND DIRECTION BASED ON IMAGE PROCESSING INFORMATION
    Publication number: 20160260221
    Abstract: A image processing method includes computing an initial phase corresponding to a difference between a position of a first pixel of an input image and a position of a first pixel of an output image using at least one of scaling ratio information between the input and output images, chroma subsampling format conversion information applied between the input and output images, or rotation angle information of the input image, and determining the position of the first pixel of the output image based on the initial phase and the position of the first pixel of the input image.
    Type: Application
    Filed: March 1, 2016
    Publication date: September 8, 2016
    Inventors: SEONG WOON KIM, Sung Chul Yoon, Ha Na Yang
  • Multimedia system and operating method of the same
    Patent number: 9424807
    Abstract: A multimedia system includes a main special function register (SFR) configured to store SFR information; a plurality of processing modules each configured to process frames of data, based on the SFR information; and a system control logic configured to control operations of the main SFR and the plurality of processing modules. The plurality of processing modules may process data of different frames at the same time period.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: August 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Han Lee, Sung Hoo Choi, Jae Sop Kong, Sung Chul Yoon, Kee Moon Chun
  • METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING SELF-ALIGNED SPACERS TO PROVIDE FINE PATTERNS
    Publication number: 20160233104
    Abstract: A method of forming a semiconductor pattern can include providing an etching target layer. A hard mask pattern can be formed on the etching target layer using photolithography. First spacers can be formed on opposing sidewalls of the hard mask pattern and the hard mask pattern can be removed from between the first spacers to provide a first double patterning pattern self-aligned to the hard mask pattern. The planarization of top surfaces of the first double patterning pattern can be increased to provide a smoothed first double patterning pattern.
    Type: Application
    Filed: December 21, 2015
    Publication date: August 11, 2016
    Inventors: NAM-GUN KIM, JINYOUNG KIM, JONGCHEON KIM, CHANMl LEE, SUNGGIL CHOI, HYUN-CHUL YOON
  • Image processing method and apparatus therefor
    Patent number: 9384574
    Abstract: Provided is an image processing method. The image processing method includes obtaining at least one stencil mask region for a current frame, obtaining a first velocity field corresponding to a radial spreading from a central point of the at least one stencil mask region, obtaining a final velocity field for the at least one stencil mask region based on the first velocity field, determining a pixel value included in the at least one stencil mask region based on the obtained final velocity field, and displaying the current frame according to the determined pixel value.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-chul Yoon, Soo-wan Park, Seung-ho Shin, Joon-seok Lee, Tae-kwon Jang, Kang-sik Choi, In-cheol Park
  • DISPLAY CONTROLLER AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME
    Publication number: 20160189665
    Abstract: A display controller includes a first register set by an open operating system, a second register set by a secure operating system, a first data input circuit configured to read normal data according to set information in the first register, a second data input circuit configured to read secure data according to set information in the second register, and a data processor configured to blend and output the normal data with the secure data to display the secure data over the normal data.
    Type: Application
    Filed: December 30, 2015
    Publication date: June 30, 2016
    Inventors: Kyoung Man Kim, Sung Chul Yoon, Xiangyu Meng
  • IMAGE PROCESSOR, METHOD OF OPERATING THE SAME, AND APPLICATION PROCESSOR INCLUDING THE SAME
    Publication number: 20160163020
    Abstract: An image processor, an application processor, a method of operating an image processor, and a chips set of an image processor are provided. The image processor includes a scaler configured to perform scaling on an input image and generate a scaled input image; and a selection circuit configured to transmit the scaled input image to either a low latency memory or a high density memory according to a memory selection signal. The application processor includes a memory configured to store an input image; and an image processor configured to scale the input image, wherein the image processor comprises a scaler configured to perform scaling on the input image and generate a scaled input image and a selection circuit configured to transmit the scaled input image to either a low latency memory or a high density memory according to a memory selection signal.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 9, 2016
    Inventors: Seong Woon KIM, Sung Chul YOON, Sang Hoon LEE, Ha Na YANG
  • Apparatus for purifying wastewater and method thereof
    Patent number: 9346695
    Abstract: The present inventions relates to an apparatus for purifying wastewater and a method thereof, which comprises: a stirring part to make bubbles impregnated into floc through high speed stirring by adding floc forming materials to influent and stirring them; an air supply part to supply air to the stirring part to make more bubbles impregnated; a pumping part to conduct pressurized conveying of the floc included treatment water; a cyclone part to separate high density floc to downstream and treatment water with low density floc to upstream from the pressurized treatment water; and a flotation part to separate floc from the treatment water with floc supplied from the cyclone part. Therefore, the present invention have an effect that it is possible to improve purification speed of wastewater and obtain good quality of purified water.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: May 24, 2016
    Assignees: POSCO ENGINEERING & CONSTRUCTION CO., LTD., BLUEGREENLINK CO., LTD.
    Inventors: Joo Hyung Ko, Kwan Yeop Kim, Yun Jung Kim, Hyun Bae Kim, Hyoung Gun Kim, Hae Wook Nam, Hee Chul Yoon, Yu Seong Won, Jae Woong Park, Young Hwa Choi
  • APPARATUS FOR SYNTHESIZING AMMONIA
    Publication number: 20160138176
    Abstract: The present disclosure relates to an ammonia synthesis apparatus, and more particularly, to an electrochemical ammonia synthesis apparatus using an aqueous solution or a molten liquid of an alkali metal as an electrolyte. According to one or more embodiments, when an aqueous solution or a molten liquid of an alkali metal is used as an electrolyte in an ammonia synthesis apparatus, compositions, sizes, and shapes of an electrode and an electrolyte may be easily controlled, and thus a yield of ammonia synthesis may improve.
    Type: Application
    Filed: September 30, 2015
    Publication date: May 19, 2016
    Inventors: Chung-yul Yoo, Hyung-chul Yoon, Ji-haeng Yu, Jong Hoon Joo, Jong-nam Kim
  • Methods and systems for providing geotemporal graphs
    Patent number: 9341486
    Abstract: Technology for generating geotemporal graphs is disclosed where geotemporal graphs provide representations of areas based on an expected travel time between points, instead of the geographical distance between points. Travel times may vary based on travel conditions, and geotemporal maps may be generated that show travel times that account for travel conditions. Generating geotemporal maps may include obtaining a graph, determining for several points a warp vector indicating graph how each point should be moved to represent a travel time to that point, and warping the graph according to the determined warp vectors.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: May 17, 2016
    Assignee: University of Washington through its Center for Commercialization
    Inventors: Cecilia Aragon, Sungsoo Hong, Jong-Chul Yoon
  • IMAGE PROCESSING CIRCUIT AND METHODS FOR PROCESSING IMAGE ON-THE-FLY AND DEVICES INCLUDING THE SAME
    Publication number: 20160125567
    Abstract: An application processor includes an image processing circuit configured to process an image on-the-fly. The image processing circuit includes N pipelines, where N is a natural number of at least 2, and an enable control circuit configured to receive first information indicating a size of the image stored in a memory and second information indicating whether the image rotates and to enable M pipelines among the N pipelines based on the first information and the second information, where 2?M?N. The enabled M pipelines divide the image into M image segments and process the M image segments in parallel.
    Type: Application
    Filed: July 31, 2015
    Publication date: May 5, 2016
    Inventors: SUNG CHUL YOON, MIN SOO KIM
  • SENSOR FOR DETECTING SACCHARIDE AND MANUFACTURING METHOD THEREOF AND DETECTION METHOD OF GLYCATED HEMOGLOBIN USING THE SAME
    Publication number: 20160109370
    Abstract: The present disclosure relates to a sensor for detecting saccharide and manufacturing method thereof and detection method of glycated hemoglobin using the same wherein the sensor for detecting saccharide includes a reactive layer synthesized with hydrogel having a boronic acid-modified 3D mesh structure. A selective and sensitive detection of the glycated protein including glucose or glycated hemoglobin (HbA1c) in blood through high level of signal may be enabled, and the durability of the sensor for detecting saccharide may be enhanced.
    Type: Application
    Filed: March 11, 2015
    Publication date: April 21, 2016
    Applicants: LG ELECTRONICS INC., AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Yunhee KU, Moosub KIM, Yongju YANG, Seung Yeon SONG, Kang Sun LEE, Hyun Chul YOON, Yong Duk HAN, Yoo Min PARK
  • SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR
    Publication number: 20160104671
    Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
    Type: Application
    Filed: December 15, 2015
    Publication date: April 14, 2016
    Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
  • APPLICATION PROCESSOR SHARING RESOURCE BASED ON IMAGE RESOLUTION AND DEVICES INCLUDING SAME
    Publication number: 20160098812
    Abstract: An application processor includes a first scaler including a first vertical scaler and a first horizontal scaler, and a second scaler including a second vertical scaler and a second horizontal scaler, wherein the second vertical scaler is selectively shared between the first scaler and the second scaler in response to a determination of resolution for an image being processed.
    Type: Application
    Filed: September 4, 2015
    Publication date: April 7, 2016
    Inventors: SANG CHUL YOON, SEONG WOON KIM, SANG HOON LEE
  • APPLICATION PROCESSOR INCLUDING RECONFIGURABLE SCALER AND DEVICES INCLUDING THE PROCESSOR
    Publication number: 20160086307
    Abstract: An application processor includes a reconfigurable hardware scaler which includes dedicated circuits configured to perform different scaling techniques, respectively and a shared circuit configured to be shared by the dedicated circuits. One of the different scaling techniques is performed by one of the dedicated circuits and the shared circuit.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 24, 2016
    Inventors: Sung Chul YOON, Ha Na YANG
  • Apparatus and method for providing emergency alert service in portable terminal
    Patent number: 9275539
    Abstract: An apparatus and method for providing an emergency alert service in a portable terminal and for generating an alarm for the emergency alert service are provided. The method includes detecting, by a controller, an SOS execution signal while the portable terminal is being operated in a certain mode, identifying, by the controller, a current operating mode of the portable terminal in response to the SOS execution signal, outputting a control signal according to the identified operating mode to a source audio signal processor, and outputting, by the source audio signal processor, a source audio signal according to an input port receiving the control signal.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: March 1, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Gu Kim, Sang Hoon Kim, Dong Sub Kim, Yong Chul Yoon
  • Semiconductor memory device and sense amplifier control method thereof
    Patent number: 9269420
    Abstract: A semiconductor memory device is provided. A cell array includes a DRAM cell connected to one of a pair of bit lines. A bit line sense amplifier is coupled to the pair of bit lines. The bit line sense amplifier discharges a low-level bit line of the pair of bit lines toward a ground level and clamps the low-level bit line to a boosted sense ground voltage in response to a control signal. A sense amplifier control logic generates the control signal having a pulse interval. The low-level bit line is discharged toward the ground level for the pulse interval and after the pulse interval ends, the low-level bit line is clamped to the boosted sense ground voltage.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: February 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kichul Chun, Hyun-Chul Yoon
  • COMPOSITION FOR MAKING HARD COATING LAYER
    Publication number: 20160046830
    Abstract: The present invention relates to a composition for forming a hard coating layer, which may form a hard coating layer having significantly improved hardness as well as excellent flexibility such that curling is minimized.
    Type: Application
    Filed: August 12, 2015
    Publication date: February 18, 2016
    Inventors: Won-Yeob KIM, Chul-Soon MOON, Hye-Jin KIM, Ho-Chul YOON, Jae-Eun LEE, Jong-Nam AHN, Young-June PARK
  • PADS INCLUDING CURVED SIDES AND RELATED ELECTRONIC DEVICES, STRUCTURES, AND METHODS
    Publication number: 20160027787
    Abstract: An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.
    Type: Application
    Filed: September 8, 2015
    Publication date: January 28, 2016
    Inventors: Je-Min Park, Seok-Hyun Lim, Tae-Yong Song, Hyun-Chul Yoon, Yoo-Sang Hwang, Hyeon-Ok Jung
  • COMPOSITION FOR MAKING HARD COATING LAYER
    Publication number: 20160024348
    Abstract: A composition for forming a hard coating layer includes an epoxy siloxane resin having a weight average molecular weight in the range of 2,000 to 15,000 and a polydispersity index (PDI) in the range of 2.0 to 4.0, and thus may form a hard coating layer having significantly improved hardness as well as excellent flexibility such that bending deformation is minimized.
    Type: Application
    Filed: July 27, 2015
    Publication date: January 28, 2016
    Inventors: Won-Yeob KIM, Hye-Jin KIM, Ho-Chul YOON, Young-June PARK
  • Semiconductor devices including bit line contact plug and peripheral transistor
    Patent number: 9231104
    Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho