Abstract: A method of making a semiconductor device includes patterning a conductive layer over a substrate to define a conductive pad having a first width. The method includes depositing a passivation layer, wherein the passivation layer directly contacts the conductive pad. The method includes depositing a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The method includes depositing an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The method includes depositing a mask layer over the UBM layer; and forming an opening in the mask layer wherein the opening has the second width. The method includes forming a conductive pillar in the opening on the UBM layer; and etching the UBM layer using the conductive pillar as a mask, wherein the etched UBM layer has the second width.

Abstract: A compound is disclosed that has a metal coordination complex structure having at least two ligands coordinated to the metal; wherein the compound has a first substituent R1 at one of the ligands' periphery; wherein a first distance is defined as the distance between the metal and one of the atoms in R1 where that atom is the farthest away from the metal among the atoms in R1; wherein the first distance is also longer than any other atom-to-metal distance between the metal and any other atoms in the compound; and wherein when a sphere having a radius r is defined whose center is at the metal and the radius r is the smallest radius that will allow the sphere to enclose all atoms in the compound that are not part of R1, the first distance is longer than the radius r by at least 2.9 ?.

Abstract: Disclosed herein is a server management apparatus, comprising: a server information acquisition unit configured to acquire, from a plurality of servers respectively, server information on a server and hardware component information on hardware components included in the server, using an identifier of a control board of the server as a key; an analysis unit configured to analyze the server information and the hardware component information, and acquire information indicating whether or not firmware of any of the server and the hardware components needs to be updated; and a structured file generation unit configured to generate a structured file that hierarchically stores, in a readable format, the server information and the hardware component information, the structured file including a header describing the information indicating whether or not the firmware of any of the server and the hardware components needs to be updated.

Abstract: Disclosed herein is a server management apparatus, comprising: a server information acquisition unit configured to acquire, from a plurality of servers respectively, server information on a server and hardware component information on hardware components included in the server, using an identifier of a control board of the server as a key; an analysis unit configured to analyze the server information and the hardware component information acquired by the server information acquisition unit, and generate a server status flag indicating whether or not any of the server and the hardware components has an abnormality; and a structured file generation unit configured to generate a structured file that hierarchically stores, in a human-readable format, the server information and the hardware component information acquired by the server information acquisition unit, the structured file including a header describing the server status flag generated by the analysis unit.

Abstract: The present disclosure provides intelligent radio frequency interference mitigation in a computing platform. The computing platform includes a processor, a memory, a system clock and a wireless network interface. The system clock can be controlled so that the processor and/or the memory may operate at a slow frequency or a fast frequency. The wireless network may operate on a radio channel that experiences radio frequency interference at the fast frequency. The system clock may be intelligently controlled to select the slow frequency to reduce radio frequency interference to prioritize execution of a network application, or to select the fast frequency to increase processor speed and prioritize execution of a local application.

Abstract: A device includes a substrate, a first nanostructure device, a second nanostructure device, a dielectric fin, an isolation structure, and first and second dielectric gate structures. The substrate has a first device region, a second device region, and a connecting region. The first nanostructure device is over the first device region. The second nanostructure device is over the second device region. The dielectric fin is over the first device region and the connecting region and is in contact with a gate structure of the first nanostructure device. The isolation structure is over the second device region and is in contact with the second nanostructure device and the dielectric fin. The first dielectric gate structure is over the substrate and between the first device region and the connecting region. The second dielectric gate structure is over the substrate and between the second device region and the connecting region.

Abstract: An electronic device includes a device body and an antenna module disposed in the device body and including a conductive structure and a coaxial cable including a core wire, a shielding layer wrapping the core wire, and an outer jacket wrapping the shielding layer. The conductive structure includes a structure body and a slot formed on the structure body and penetrating the structure body in a thickness direction of the structure body. A section of the shielding layer extends from the outer jacket and is connected to the structure body. A physical portion of the structure body and the section of the shielding layer are respectively located on two opposite sides of the slot in a width direction of the slot. A section of the core wire extends from the section of the shielding layer and overlaps the slot and the physical portion in the thickness direction.

Abstract: A method to establish and activate an MA PDU session for data transmission over a selected access is proposed. UE initiates a UE-requested PDU session establishment procedure. Once the UE receives a PDU SESSION ESTABLISHMENT ACCEPT message with ATSSS container IE, the UE can consider the MA PDU session has been activated and user plane resources are successfully established on the selected access. A method to convert an SA PDU session to an MA PDU session for data transmission over a selected access is proposed. UE initiates a UE-requested PDU session modification procedure. Once the UE receives a PDU SESSION MODIFICATION COMMAND message with ATSSS container IE, the UE can consider the MA PDU session has been converted from the SA PDU session and user plane resources are successfully established on the selected access.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. In certain configurations, the UE enters a first radio resource control (RRC) connection with a first base station of a first network. The UE receives, from the first base station, an indication that enables the UE to send a first request for deactivating or releasing resources used for communications with the first base station. In response to a determination to enter a second RRC connection with a second base station of a second network, the UE sends, to the first base station, the first request for deactivating or releasing the resources. The UE enters the second RRC connection with the second base station while maintaining the first RRC connection with the first base station.

Abstract: Novel Pt tetradentate complexes having Pt—O bond is disclosed. These complexes are useful as emitters in phosphorescent OLEDs.

Abstract: A laser inspection system is provided. A laser source emits a laser with a first spectrum and the laser is transmitted by a first optical fiber. A gain optical fiber doped with special ions is connected to the first optical fiber, and a light detector is provided around the gain optical fiber. When the laser with the first spectrum passes through the gain optical fiber, the gain optical fiber absorbs part of the energy level of the laser with the first spectrum, so that the laser with the first spectrum is converted to generate light with a second spectrum based on the frequency conversion phenomenon. The light detector detects the intensity of the light with the second spectrum, so that the power of the laser source can be obtained.

Abstract: Fluorine substituted metal complexes as efficient phosphorescent emitters is disclosed. The fluorine substitution is at para position of a phenyl group.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.

Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

Abstract: A display may include an array of pixels. A pixel can include an organic light-emitting diode, up to three thin-film transistors, and up to two capacitors. The pixel can include a drive transistor, an emission transistor, and a select transistor. The select transistor can be used to apply a reference voltage to the gate of the drive transistor during a global reset phase and during a global threshold voltage sampling phase and can also be used to apply a data voltage to the gate of the drive transistor during a data programming phase. The drive transistor can receive a power supply voltage that toggles between a low voltage during the global reset phase and a high voltage during other phases of operation. Configured and operated in this way, the pixel need not include separate dedicated anode reset and initialization transistors.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.

Abstract: An embodiment interfacial bonding test structure may include a first substrate having a first planar surface, a second substrate having a second planar surface that is parallel to the first planar surface, a first semiconductor die, and a second semiconductor die, each semiconductor die bonded between the first substrate and the second substrate thereby forming a sandwich structure. The first semiconductor die and the second semiconductor die may be bonded to the first surface with a first adhesive and may be bonded to the second surface with a second adhesive. The first semiconductor die and the second semiconductor die may be displaced from one another by a first separation along a direction parallel to the first planar surface and the second planar surface. The second substrate may include a notch having an area that overlaps with an area of the first separation in a plan view.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: An image sensor structure includes a semiconductor substrate, a plurality of image sensing elements, a reflective element, and a high-k dielectric structure. The image sensing elements are in the semiconductor substrate. The reflective element is in the semiconductor substrate and between the image sensing elements. The high-k dielectric structure is between the reflective element and the image sensing elements.