Abstract: A device and method for generating article markup information are provided. The method for generating article markup information includes the following. Segmentation processing is performed on an article to generate a segmentation result. Name entity recognition is performed on the segmentation result to generate a first recognition result. Whether the segmentation result includes any word in an expansion list is determined. Expanded entity classification conversion is performed on the first recognition result to generate a second recognition result. The second recognition result and the segmentation result are used as markup information.

Abstract: A semiconductor device includes a substrate, a first stack of semiconductor nanosheets, a second stack of semiconductor nanosheets, a gate structure and a first dielectric wall. The substrate includes a first fin and a second fin. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets is disposed on the second fin. The gate structure wraps the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall is disposed between the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall includes at least one neck portion between adjacent two semiconductor nanosheets of the first stack.

Abstract: A multi-projector system and a method of calibrating the multi-projector system are provided. The method includes: controlling a first projector to project a first image, and capturing and generating a first captured image including the first image to obtain a first color value from the first captured image through an image capturing device; projecting a second image according to a first projection parameter, and capturing and generating a second captured image including the second image to obtain a second color value from the second captured image through the image capturing device, wherein the first projection parameter includes an electrical parameter of a light source module of the second projector; calculating an absolute difference between the first color value and the second color value; and adjusting the first projection parameter to update the absolute difference in response to the absolute difference being greater than a first threshold.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: A trimming method is provided. The trimming method includes the following steps. A first wafer including a substrate and a device layer over a first side of the substrate is provided. The first wafer is bonded to a second wafer with the first side of the substrate facing toward the second wafer. An edge trimming process is performed to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate, wherein the edge trimming process results in the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction.

Abstract: A fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.

Abstract: Semiconductor devices are provided. A semiconductor device includes a first well region having a first conductivity type, a second well region having a second conductivity type, a cell, and a pickup tap cell. The cell includes a first forksheet structure. The first forksheet structure includes a first transistor formed over the first well region, a second transistor formed over the second well region, and a first wall structure disposed on and extending along an interface between the first and second well regions. The first transistor and the second transistor are disposed on opposite sides of the first wall structure. The pickup tap cell includes a nanosheet structure. The nanosheet structure includes a pickup transistor formed over the second well region. Source/drain features of the first transistor and the pickup transistor have the second conductivity type, and source/drain features of the second transistor have the first conductivity type.

Abstract: A protecting method for preventing solder crack failure in an electronic product is provided. Firstly, a step (a) is performed to confirm that a crack incidence rate of a metallic solder material in a printed circuit board is high. In a step (b), a protecting mechanism of controlling the electronic product to enter an idle mode and leave the idle mode is activated. Consequently, an operating temperature of the electronic product decreases at a first average drop rate.

Abstract: Disclosed is an electronic device including a device body and an antenna module. The antenna module includes a conductive element and at least one antenna element. The conductive element includes a main body portion and at least one assembly portion connected with each other. The at least one assembly portion is assembled on the device body. The at least one antenna element is disposed on the device body and coupled with the conductive element to excite a first resonance mode. The at least one assembly portion overlaps the at least one antenna element in the length direction of the main body portion.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Abstract: Provided is a graphene-based coating suspension comprising multiple graphene sheets, thin film coating of an anti-corrosive pigment or sacrificial metal deposited on graphene sheets, and a binder resin dissolved or dispersed in a liquid medium, wherein the multiple graphene sheets contain single-layer or few-layer graphene sheets selected from a pristine graphene material having essentially zero % of non-carbon elements, or a non-pristine graphene material having 0.001% to 47% by weight of non-carbon elements wherein the non-pristine graphene is selected from graphene oxide, reduced graphene oxide, graphene fluoride, graphene chloride, graphene bromide, graphene iodide, hydrogenated graphene, nitrogenated graphene, doped graphene, chemically functionalized graphene, or a combination thereof. The invention also provides a process for producing this coating suspension. Also provided is an object or structure coated at least in part with such a coating.

Abstract: A bracket is provided. The bracket includes a fixing seat and a holding seat. The fixing seat has a first extending direction and includes at least one first contacting end surface, and a first angle is contained between the at least one first contacting end surface and the first extending direction. The holding seat is detachably connected to the fixing seat with a bend angle to form a bend structure, and the holding seat includes at least one second contacting end surface corresponding to the at least one first contacting end surface. The at least one first contacting end surface and the at least one second contacting end surface are located near or at a bend portion of the bend structure.

Abstract: A micro light-emitting diode is provided. The micro light-emitting diode includes a first-type semiconductor layer having a first doping type; a light-emitting layer over the first-type semiconductor layer; a first-type electrode over the first-type semiconductor layer; a second-type semiconductor layer having a second doping type over the light-emitting layer, wherein the second doping type is different from the first doping type; a second-type electrode over the second-type semiconductor layer; and a barrier layer under the first-type semiconductor layer and away from the first-type electrode and the second-type electrode, wherein the barrier layer includes a doped region having the second doping type.

Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.

Abstract: A compound is disclosed that has a metal coordination complex structure having at least two ligands coordinated to the metal; wherein the compound has a first substituent R1 at one of the ligands' periphery; wherein a first distance is defined as the distance between the metal and one of the atoms in R1 where that atom is the farthest away from the metal among the atoms in R1; wherein the first distance is also longer than any other atom-to-metal distance between the metal and any other atoms in the compound; and wherein when a sphere having a radius r is defined whose center is at the metal and the radius r is the smallest radius that will allow the sphere to enclose all atoms in the compound that are not part of R1, the first distance is longer than the radius r by at least 2.9 ?.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: A method of making a semiconductor device includes patterning a conductive layer over a substrate to define a conductive pad having a first width. The method includes depositing a passivation layer, wherein the passivation layer directly contacts the conductive pad. The method includes depositing a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The method includes depositing an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The method includes depositing a mask layer over the UBM layer; and forming an opening in the mask layer wherein the opening has the second width. The method includes forming a conductive pillar in the opening on the UBM layer; and etching the UBM layer using the conductive pillar as a mask, wherein the etched UBM layer has the second width.