Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Abstract: Techniques for nurturing content creation are provided. In one technique, a particular user is identified. Candidate entities are identified based on one or more attributes of the particular user. For each candidate entity, a feedback sensitivity measure of content creation of the candidate entity is determined. The feedback sensitivity measure is generated based on an amount of feedback, from other users, to content that the candidate entity has created. A score is then generated for the candidate entity based on the measure. A ranking of the candidate entities is determined based on the score of each candidate entity. A subset of the candidate entities is selected based on the ranking. The subset of the candidate entities is transmitted over a computer network to be presented on a computing device of the particular user.

Abstract: A degradable aroma product with seeds wrapped therein includes plant seeds and growth carriers coated or mixed with plant nutrients and aromatizers. The degradable aroma product may be in the form of an aroma card with the growth carriers being made of paper pulp, or alternatively, in the form of an aroma sachet with the plant seeds and the growth carriers or the aroma card wrapped in a degradable packaging bag. When the degradable aroma product has been used over a period of time and no longer produces fragrance, it can be directly buried in soil without forming any pollutant and accordingly, meets the requirement of plastic and waste reduction. Further, with the plant nutrients, the plant seeds can grow into trees, flowers or fruits more easily to enable sustainable development of healthy circle of life (i.e. the product design concept of cradle-to-cradle), carbon reduction and environmental protection.

Abstract: Provided are an enzymatic reaction composition, a method for increasing the amount of adenosine triphosphate (ATP) in an enzymatic reaction, and a method for synthesizing amino acids or derivatives thereof, polypeptides, enzymes or proteins by using ATP. In the method, a first enzyme or enzyme group for producing adenosine monophosphate (AMP) is added during the enzymatic reaction so as to additionally increase the amount of ATP.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: A plastic light-folding element includes an incident surface, an exit surface, at least one reflective surface, at least one connecting surface and at least one gate vestige structure. The incident surface is configured to lead an imaging light enter the plastic light-folding element. The exit surface is configured to lead the imaging light exit the plastic light-folding element. The reflective surface is configured to fold the imaging light. The connecting surface is connected to the incident surface, the exit surface and the reflective surface. The gate vestige structure is disposed on the connecting surface. At least one of the incident surface, the exit surface and the reflective surface includes an optical portion and an arc step structure, the arc step structure is disposed on a periphery of the optical portion, and an arc is formed by the arc step structure centered on the optical portion.

Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: A compound of the formula (1) exhibits high photoluminescence quantum yields, high radiative decay constant and low ASE thresholds from solution-processed neat and blend films. Ar1 and Ar2 are aryl groups, L is a divalent group having a group of the formula (2), and R is H or a diarylamino group. At least one alkyl group having at least five carbon atoms which are bonded is present in the formula (1).

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: Methods, systems, and computer program products are described for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design. These netlists provide RTL design information corresponding to a portion of a semiconductor device. A configuration tracer generates behavior information associated with the RTL design. A register compiler compiles a set of semiconductor devices based on one or more technologies and power, performance, and area (PPA) information related to the semiconductor device. Semiconductor devices generated by the register compiler that meet predefined power, performance, and area conditions are identified. Structural information for aligning the input/output ports of the semiconductor device is generated.

Abstract: Provided are co-crystals of a sodium benzoate compound and a co-former compound of Formula (I) Also provided herein are methods of preparing the co-crystals and uses thereof in treating and/or reducing the risk for a neuropsychiatric disorder (e.g., schizophrenia, psychotic disorders, depressive disorders, or Alzheimer's disease) or a glucose or lipid metabolic disorder (e.g., obesity, diabetes, hypercholesterolemia, hypertension, or hyperlipidemia).

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: An image calibration method for imaging system is provided, including: specifying a detection area located in an image capture scope and the detection area having a unit to be tested; capturing a detection image respectively when the detection area is located in at least two locations within the image capture scope; combining the plurality of detection images and calculating to obtain a calibration figure; and applying the calibration figure to a captured image to complete the calibration. In this way, the calibration figure that adapt to the luminescent type and size of the unit to be tested can be obtained.

Abstract: Techniques for nurturing content creation are provided. In one technique, a particular user is identified. Candidate entities are identified based on one or more attributes of the particular user. For each candidate entity, a feedback sensitivity measure of content creation of the candidate entity is determined. The feedback sensitivity measure is generated based on an amount of feedback, from other users, to content that the candidate entity has created. A score is then generated for the candidate entity based on the measure. A ranking of the candidate entities is determined based on the score of each candidate entity. A subset of the candidate entities is selected based on the ranking. The subset of the candidate entities is transmitted over a computer network to be presented on a computing device of the particular user.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.