Abstract: An ADC calibration system includes a clock generating circuit, under test ADCs, a standard ADC, and a calibration circuit. The clock generating circuit generates operation clocks according to a system clock, and generates a calibration clock according to the system clock and a selection signal. The under test ADCs sample an input signal according to the operation clocks to output under test sampling results. The standard ADC samples the input signal according to the calibration clock to output a standard sampling result. The calibration circuit makes the phases of the calibration clock and a first operation clock received by a first ADC to be the same. The calibration circuit compares the standard sampling result with a first under test sampling result to generate calibration information corresponding to the first under test sampling result, and calibrates the first under test sampling result according to the calibration information.

Abstract: A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region.

Abstract: A microwave modulation device includes a first radiator, a second radiator and a modulation structure. The first radiator includes a substrate; a metal layer disposed on the substrate; a protective layer disposed on at least a portion of the metal layer and including a through hole overlapping with at least a portion of the metal layer; and an etch stop layer disposed between the metal layer and the protective layer. The second radiator disposed corresponding to the first radiator. The modulation structure is disposed between the first radiator and the second radiator.

Abstract: A panel laminating method is provided with the following steps. A transparent adhesive layer is formed on a first panel. At least a portion of the transparent adhesive layer is pre-cured to increase the viscosity of the transparent adhesive layer. After the transparent adhesive layer is pre-cured, a second panel is stacked on the transparent adhesive layer. After the second panel is stacked on the transparent adhesive layer, the entire of the transparent adhesive layer is main-cured so that the second panel is laminated to the first panel through the transparent adhesive layer. Besides, a panel assembly and an electronic device are also provided.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: The filtration material includes a supporting layer, a first selective layer disposed on the supporting layer, and a second selective layer disposed on the first selective layer. The first selective layer includes a polyimide and an ionic polymer intertwined with the polyimide. In particular, the polyimide includes at least one repeat unit having a structure represented by Formula (I) wherein A1 is A2 is R1 and R2 are independently —H, —CF3, —OH, —Br, —Cl, —F, C1-6 alkyl group, or C1-6 alkoxy group; and X and Y are independently single bond, —O—, —CH2—, —C(CH3)2—, or —NH—.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: The presently disclosed subject matter provides methods and compositions for activation of clustered receptors on a target cell using nanocarrier-associated ligands, particularly methods and compositions for targeted activation of clustered receptors on antigen-experienced T cells using nanocarrier-associated antibodies.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: Provided is a FinFET device including a substrate having at least one fin of the FinFET device, a gate stack, a spacer, a strained layer, a composite etching stop layer, a dielectric layer and a connector. The gate stack is across the at least one fin of the FinFET device. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer. The dielectric layer is on the composite etching stop layer. The connector is over and electrically connected to the strained layer. A first upper portion of a first sidewall of the connector is in contact with the composite etching stop layer, and a second upper portion of a second sidewall of the connector is separate from the composite etching stop layer by the dielectric layer therebetween.

Abstract: An electronic assembly includes a transparent adhesive layer, a transparent cover, a display module and a frame. The transparent adhesive layer has a first adhesive surface and a second adhesive surface opposite to the first adhesive surface, the second adhesive surface having a central region and a peripheral region around the central region. The transparent cover is adhered to the first adhesive surface of the transparent adhesive layer. The display module is adhered to the central region of the transparent adhesive layer. The frame has a border carrying part which is adhered to the peripheral region of the transparent adhesive layer.

Abstract: The present disclosure discloses a nasogastric tube used to insert into a patient's body from nose to stomach. The patient's body from nose to stomach comprises a posterior pharyngeal wall, an inferior conch, a nasopharynx rear-upper wall, and a soft palate; the nasogastric tube comprises a tube body and a pressurized structure. The tube body has a longitudinal direction and includes a proximal end and a distal end. A distance is between and the posterior pharyngeal wall. The pressurized structure is disposed on the tube body along the longitudinal direction and near the distal end. The pressurized structure comprises a cavity. When a fluid is filled into the cavity, the pressurized structure is pressurized; and the distal end is lifted to reduce the distance to the posterior pharyngeal wall.

Abstract: Provided is a FinFET device including a substrate having at least one fin, a gate stack, a spacer, a strained layer and a composite etching stop layer. The gate stack is across the at least one fin. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer.

Abstract: The present disclosure provides a wireless Ethernet network controlling method, for connecting a mobile device to an Ethernet through a wireless dock, comprising: connecting an Ethernet PHY of a wireless dock to an Ethernet; wirelessly linking a first wireless NIC of the wireless dock to a second wireless NIC of a mobile device; a control server unit of the wireless dock receiving an operation status setting signal through the first wireless NIC generated by a virtual Ethernet NIC, and the control server unit transmitting the operation status setting signal to the Ethernet PHY for setting-up the operation status of the Ethernet PHY; and a VLAN unit processing the data packets transmitted between the Ethernet PHY and the first wireless NIC. Accordingly, the user of the mobile device can experience the complete functions of the Ethernet device.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: A detection method for a touch panel is provided. The method includes the following steps: (a) using a transfer device to move the touch panel; (b) placing the touch panel on an LCD monitor; (c) emitting at least one striped light pattern from the LCD monitor; (d) using at least one camera to capture an image that is formed by the at least one striped light pattern through the touch panel; and (e) using a processor to analyze the image to complete the detection of the touch panel.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.

Abstract: Provided is a FinFET device including a substrate having at least one fin, a gate stack, a spacer, a strained layer and a composite etching stop layer. The gate stack is across the at least one fin. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer.

Abstract: The filtration material includes a supporting layer, a first selective layer disposed on the supporting layer, and a second selective layer disposed on the first selective layer. The first selective layer includes a polyimide and an ionic polymer intertwined with the polyimide. In particular, the polyimide includes at least one repeat unit having a structure represented by Formula (I) wherein A1 is A2 is R1 and R2 are independently —H, —CF3, —OH, —Br, —Cl, —F, C1-6 alkyl group, or C1-6 alkoxy group; and X and Y are independently single bond, —O—, —CH2—, —C(CH3)2—, or —NH—.