Abstract: Provided is a FinFET device including a substrate having at least one fin, a gate stack, a spacer, a strained layer and a composite etching stop layer. The gate stack is across the at least one fin. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer.

Abstract: The filtration material includes a supporting layer, a first selective layer disposed on the supporting layer, and a second selective layer disposed on the first selective layer. The first selective layer includes a polyimide and an ionic polymer intertwined with the polyimide. In particular, the polyimide includes at least one repeat unit having a structure represented by Formula (I) wherein A1 is A2 is R1 and R2 are independently —H, —CF3, —OH, —Br, —Cl, —F, C1-6 alkyl group, or C1-6 alkoxy group; and X and Y are independently single bond, —O—, —CH2—, —C(CH3)2—, or —NH—.

Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: A composite fiber capillary structure includes a first interlacing layer and a second interlacing layer. The first interlacing layer is formed as a hollow cylindrical net structure by metal wires with a first diameter. The second interlacing layer is also formed as a hollow cylindrical net structure by metal wires with a second diameter. The first diameter is larger than the second diameter, and the second interlacing layer covers the first interlacing layer in a sleeving manner. In addition, a fabricating method of the composite fiber capillary structure and a heat pipe with the composite fiber capillary structure are also provided.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: The presently disclosed subject matter provides methods and compositions for activation of clustered receptors on a target cell using nanocarrier-associated ligands, particularly methods and compositions for targeted activation of clustered receptors on antigen-experienced T cells using nanocarrier-associated antibodies.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.

Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.

Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

Abstract: A display module including a display panel, an optical film, a cover plate and an optical clear adhesive (OCA) layer is provided. The display panel has a display surface. The optical film is disposed on the display surface, wherein the optical film has a first surface back to the display panel, and the first surface has a plurality of edges and a plurality of corners formed by any adjacent two of the edges crossing each other. The cover plate is disposed on the first surface of the optical film and covers the first surface. The OCA layer is disposed between the cover plate and the optical film and connected with the cover plate and the optical film, wherein the OCA layer covers the edges of the first surface and exposes the corners and a part of regions adjacent to the corners.

Abstract: A detection method for a touch panel is provided. The method includes the following steps: (a) using a transfer device to move the touch panel; (b) placing the touch panel on an LCD monitor; (c) emitting at least one striped light pattern from the LCD monitor; (d) using at least one camera to capture an image that is formed by the at least one striped light pattern through the touch panel; and (e) using a processor to analyze the image to complete the detection of the touch panel.

Abstract: The present disclosure provides a wireless Ethernet network controlling method, for connecting a mobile device to an Ethernet through a wireless dock, comprising: connecting an Ethernet PHY of a wireless dock to an Ethernet; wirelessly linking a first wireless NIC of the wireless dock to a second wireless NIC of a mobile device; a control server unit of the wireless dock receiving an operation status setting signal through the first wireless NIC generated by a virtual Ethernet NIC, and the control server unit transmitting the operation status setting signal to the Ethernet PHY for setting-up the operation status of the Ethernet PHY; and a VLAN unit processing the data packets transmitted between the Ethernet PHY and the first wireless NIC. Accordingly, the user of the mobile device can experience the complete functions of the Ethernet device.

Abstract: A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region.

Abstract: A lifting resilient garment at least including a pair of trousers and the zip-fastening devices disposed on the trousers is provided. The lifting resilient garment is formed of at least one elastic material. When the zip-fastening device is zipped up, the trouser is tightened and a first cross-sectional area (A1) of the trouser is created consequently. When the zip-fastening device is zipped down, a second cross-sectional area (A2) of the trouser is created consequently. The first cross-sectional area (A1) is smaller than the second cross-sectional area (A2).

Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.

Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.

Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.