Abstract: This invention discloses a DRAM cell includes an asymmetric transistor coupled to a capacitor. The asymmetric transistor includes a drain region extending upward from an isolator region; a gate region extends upward from a gate dielectric or the isolator; a source region of asymmetric transistor extends upward from a first portion of an isolating layer. The upward extending directions of the drain region, the gate region, and the source region are perpendicular or substantially perpendicular to an original silicon surface. Moreover, the capacitor is partially formed in a concave and the isolating layer is positioned in the concave. The capacitor extends upward from a second portion of the isolating layer. The upward extending directions of the upright portion of the capacitor electrode, the third portion of the insulating layer and the counter electrode are perpendicular or substantially perpendicular to the original silicon surface.

Abstract: An optical module includes an electronic assembly and an optical assembly. The electronic assembly includes a circuit board and a chip component. The optical assembly disposed on the electronic assembly includes a bracket and an optical component. The bracket surrounds the chip component and has at least two conductive layers separated from each other. The conductive layers are electrically connected to the electronic assembly. The optical assembly is disposed on the bracket and has at least one light-transmissive conductive layer which is electrically connected to the conductive layers.

Abstract: A liquid crystal photoelectric apparatus includes a first and a second quartz glass substrates, an upper alignment layer disposed between the first and the second quartz glass substrates, a lower alignment layer disposed between the upper alignment layer and the second quartz glass substrate, a liquid crystal material disposed between the upper and the lower alignment layers, a first transparent conductive layer disposed between the upper alignment layer and the first quartz glass substrate and including at least one first main portion and first finger portions extending from the corresponding first main portion and a second transparent conductive layer second transparent conductive layer disposed between the lower alignment layer and the second quartz glass substrate and including a second main portion and second finger portions extending from the second main portion in an extension direction perpendicular to that of the first finger portions. An optical imaging processing system is provided.

Abstract: A capacitor is provided. The capacitor includes a first electrode layer and a second electrode layer; and a first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are disposed between the first electrode layer and the second electrode layer. The first dielectric layer includes a first dielectric powder and a first organic resin, and the second dielectric layer includes a second dielectric powder and a second organic resin. In particular, the weight ratio of the first dielectric powder to the first organic resin is greater than the weight ratio of the second dielectric powder to the second organic resin.

Abstract: An optical module includes an electronic assembly and an optical component. The electronic assembly includes a chip component and a circuit board. The optical assembly disposed on the electronic assembly includes a bracket and an optical component. The bracket surrounds the chip component and has at least two conductive layers separated from each other. The conductive layers extend to the bottom of the bracket and are electrically connected to the electronic assembly. The optical assembly is disposed on the bracket and has at least one light-transmissive conductive layer which is electrically connected to the conductive layers.

Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

Abstract: A DRAM chip includes a DRAM cell and a first voltage source. The DRAM cell includes an access transistor, and one terminal of the access transistor is coupled to a word line. The first voltage source is selectively coupled to the access transistor via the word line, and generates a first voltage level higher than a sum of a threshold voltage of the access transistor and a voltage level of a signal ONE utilized in the DRAM chip. A whole access cycle includes an access operation period and a restore phase period. When the whole access cycle begins, the one terminal of the access transistor is initially applied by the first voltage level for a first portion of the access operation period and then applied by a second voltage level for a second portion of the access operation period. The second voltage level is lower than the first voltage level.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: A transistor structure includes a gate structure, a channel region, a drain region and a source region. The gate structure is positioned above a silicon surface of a first silicon material, the channel region is under the silicon surface, and the channel region includes a first terminal and a second terminal. The drain/source region is independent and not derived from the first silicon material, the drain region includes a first predetermined physical boundary directly connected to the first terminal of the channel region, and the source region includes a second predetermined physical boundary directly connected to the second terminal of the channel region. The drain/source region includes a lower portion below the silicon surface and the bottom of the lower portion of the drain/source region is confined to an isolator, and sidewalls of the drain/source region are confined to spacers except sidewalls of the lower portion of the drain/source region.

Abstract: The invention relates to a DRAM structure which comprise a capacitor set and at least a transistor. The capacitor set includes a first capacitor with a first electrode and a second capacitor with a second electrode, and a counter electrode is shared by the first and the second capacitors. The counter electrode is perpendicular or substantially perpendicular to an extension direction of an active region of the transistor, or the counter electrode is not positioned above or below the first and second electrode.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Abstract: A purifying device including a container, at least one cover, a sensing assembly and an ultraviolet source is provided. The container has a containing space, wherein the containing space is adapted to contain a liquid. The cover is adapted to be connected to the container to cover the containing space. The sensing assembly is disposed on the cover, wherein the sensing assembly is adapted to sense a usage state of the cover. The ultraviolet source is disposed on the cover and is adapted to generate an ultraviolet emitted to outside of the cover, wherein the ultraviolet source is turned on or turned off according the usage state of the cover.

Abstract: A smart power supply system is provided. An input end connecting to a power supply provides power to a control module, so that the control module can receive an application voltage range from an electronic product, and then control a power module according to the application voltage range to make an output voltage value of an output end increased gradually according to the application voltage range from low to high. In the process that the output voltage value of the output end is increased gradually, the control module detects an input voltage value and an input current value and the output voltage value to calculate and store an input power correspondingly, and then control the power module according to the output voltage value, which corresponds to the minimum input power of the stored input powers to make the output voltage value of the output end be an optimum voltage value.

Abstract: A smart power supply system is provided. An input end connecting to a power supply provides power to a control module, so that the control module can receive an application voltage range from an electronic product, and then control a power module according to the application voltage range to make an output voltage value of an output end increased gradually according to the application voltage range from low to high. In the process that the output voltage value of the output end is increased gradually, the control module detects an input voltage value and an input current value and the output voltage value to calculate and store an input power correspondingly, and then control the power module according to the output voltage value, which corresponds to the minimum input power of the stored input powers to make the output voltage value of the output end be an optimum voltage value.

Abstract: The disclosure relates to a complexed iodine-based electrolyte, a redox flow battery comprising the complexed iodine-based electrolyte, and a method for producing the redox flow battery.

Abstract: A liquid crystal photoelectric apparatus includes a first and a second quartz glass substrates, an upper alignment layer disposed between the first and the second quartz glass substrates, a lower alignment layer disposed between the upper alignment layer and the second quartz glass substrate, a liquid crystal material disposed between the upper and the lower alignment layers, a first transparent conductive layer disposed between the upper alignment layer and the first quartz glass substrate and including at least one first main portion and first finger portions extending from the corresponding first main portion and a second transparent conductive layer second transparent conductive layer disposed between the lower alignment layer and the second quartz glass substrate and including a second main portion and second finger portions extending from the second main portion in an extension direction perpendicular to that of the first finger portions. An optical imaging processing system is provided.

Abstract: A light source apparatus including a light-emitting module and a control unit is provided. The light-emitting module is configured to provide a light. The control unit is configured to make the light switched between a first light and a second light so that at least one of a blue-light hazard and a circadian stimulus value of the light is changed. A wavelength of a blue light main peak in a spectrum of the first light is different from a wavelength of a blue light main peak in a spectrum of the second light.

Abstract: An inductor structure with height limit, which comprises: a conductor formed in a bent shape, and is set with a plurality of bending-portions, wherein a first connecting-pin and a second connecting-pin are respectively set at two ends of the conductor; a first magnetic core set with a first combining-surface, wherein the first combining-surface forms a concave groove to accommodate the conductor; and a second magnetic core set with a second combining-surface, wherein the second combining-surface forms a second concave groove to accommodate the conductor; wherein the second combining-surface is combined on the first combining-surface; wherein the conductor is sheathed and set between the first magnetic core and the second magnetic core, and is set with the first connecting-pin and the second connecting-pin exposedly. Therefore, the present invention can increase the magnetic (coupling) route length under the height limit to produce an effect of increasing the inductance value and current.

Abstract: An antenna array module is provided, which includes a circuit layer, an antenna dielectric layer, a metal plate and a chip. The circuit layer includes a signal line, a ground layer and a first dielectric material; the ground layer includes a coupling slot, and the signal line is connected to the chip. The antenna dielectric layer is disposed on the circuit layer and the antenna dielectric layer includes a second dielectric material; the thermal conductivity coefficient of the second dielectric material is lower than the thermal conductivity coefficient of the first dielectric material. The metal plate is disposed on the antenna dielectric layer; the signal line is coupled to the metal plate via the coupling slot.

Abstract: This invention pertains to slurries, methods and systems that can be used in chemical mechanical planarization (CMP) of tungsten containing semiconductor device. Using the CMP slurries with additives to counter lowering of pH by tungsten polishing byproducts and maintain pH 4 or higher, the erosion of dense metal (such as tungsten) structures can be greatly diminished.