Abstract: An electric paper tray includes a base, a paper holding element pivotally mounted to at least one side of the base, a power unit arranged at the base, and a lifting module connected between the paper holding element and the power unit. The lifting module is movably mounted under the paper holding element. When the lifting module is driven by the power unit to move to a first position, with respect to the base, the lifting module drives the paper holding element to make the paper holding element rotate to a closed position, when the lifting module is driven by the power unit to move to a second position, with respect to the base, the lifting module drives the paper holding element to make the paper holding element rotate to an opened position.

Abstract: A wafer-grade LED detection device and a wafer-grade LED detection method are provided. The wafer-grade LED detection device includes a light-generating module for providing a first light beam that passes through an LED wafer to be converted into a second light beam, a light-filtering module adjacent to the LED wafer for receiving the second light beam that passes through the light-filtering module to be converted into a third light beam, and a light-detecting module adjacent to the light-filtering module for receiving and detecting the third light beam. A wavelength range of the second light beam is restricted by the light-filtering module, so that a wavelength range of the third light beam is smaller than the wavelength range of the second light beam. When the third light beam is received by the light-detecting module, the light-detecting module can detect the third light beam for obtaining relevant information.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.

Abstract: A device with a noise shaping function in gain control includes a first adder, an N-bit quantizer, a mapping circuit, a second adder, a first D flip-flop, a scaler, and a second D flip-flop. The first adder generates a first value according to an input signal, a second value, and a third value. The N-bit quantizer outputs a codeword to a controller according to the first value. Adjusting orders corresponding to codewords outputted by the N-bit quantizer are between a smallest predetermined negative value and a largest positive predetermined value, the controller utilizes an adjusting order corresponding to the codeword to make a signal generator generate a signal with adjusted power, and N is an integer greater than 2. The first D flip-flop, the scaler, and the second D flip-flop are used for providing a high-pass filter effect to the device.

Abstract: The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery.

Abstract: A feeding roller structure includes a fastening frame, a transmission component, a transmission roller and a floating coupler. The transmission component is assembled in the fastening frame. The transmission component includes a drive shaft transversely pivoted to two sides of the fastening frame. The transmission roller is concentrically arranged around the drive shaft. The floating coupler is mounted to the fastening frame. The floating coupler is coupled between the drive shaft and the transmission roller. Two opposite ends of the floating coupler are adjacent to and spaced from the two sides of the fastening frame to form two gaps. Each gap is formed between one end of the floating coupler and one side of the fastening frame. The two gaps limit an angular displacement of the floating coupler.

Abstract: The invention relates to a DRAM structure which comprise a capacitor set and at least a transistor. The capacitor set includes a first capacitor with a first electrode and a second capacitor with a second electrode, and a counter electrode is shared by the first and the second capacitors. The counter electrode is perpendicular or substantially perpendicular to an extension direction of an active region of the transistor, or the counter electrode is not positioned above or below the first and second electrode.

Abstract: A memory cell structure includes a silicon substrate, a transistor, a bit line, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The bit line is electrically coupled to the first conductive region of the transistor and positioned under the silicon surface. The capacitor is over the transistor and electrically coupled to the second conductive region of the transistor.

Abstract: A scanner includes a scanning module. The scanning module has a scan channel and a scanning glass. A lower surface of the scanner is defined as a bottom wall of the scan channel. The scanning glass is positioned above the scan channel. A bottom surface of the scanning glass is defined as a top wall of the scan channel. The lower surface of the scanner has an upstream turn connected between an upstream section and a middle section of the lower surface of the scanner, the middle section of the lower surface of the scanner is parallel with the bottom surface of the scanning glass.

Abstract: The disclosure relates to a complexed iodine-based electrolyte, a redox flow battery comprising the complexed iodine-based electrolyte, and a method for producing the redox flow battery.

Abstract: A transistor structure includes a semiconductor substrate, agate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The channel region includes a first terminal and a second terminal. The first conductive region is electrically coupled to the first terminal of the channel region, and the first conductive region includes a first metal containing region under the semiconductor surface.

Abstract: An LED wafer, an LED wafer detection device and an LED wafer detection method are provided. The LED wafer includes a wafer base, a plurality of LED chips, a plurality of positive test circuit layers, a plurality negative test circuit layers, a plurality of positive test contacts, and a plurality of negative test contacts. Each LED chip has a positive contact and a negative contact respectively electrically connected to the corresponding positive test circuit layer and the corresponding negative test circuit layer. The positive test contacts are respectively electrically connected to the positive test circuit layers, and the negative test contacts are respectively electrically connected to the negative test circuit layers. Whereby, when inputting an electric current into the positive test contacts, and then outputting the electric current from the negative test contacts, each LED chip is excited to generate a light source.

Abstract: Systems, methods, and devices are provided for providing intra-frame luminance scaling to avoid drawing excessive power while still providing exceptional brightness. An instantaneous average pixel luminance of an electronic display may be determined. The instantaneous average pixel luminance may correspond to an amount of light currently being emitted by the electronic display due to a previous image frame and a current image frame. Based at least in part on the instantaneous average pixel luminance, the luminance of a subset of pixels of image data of the current image frame may be adjusted, thereby allowing the electronic display to operate at a relatively high brightness level without exceeding a power limit.

Abstract: This invention discloses sustainable DRAM with principle power supply voltage which is unified with an external logic circuit. The DRAM circuit is configured to couple with the external logic circuit and with a principle power supply voltage source. The DRAM circuit comprises a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator generates a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM circuit. The DRAM core circuit has a DRAM cell comprising an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. Wherein, a voltage level of the principle power supply voltage source to the DRAM circuit is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.

Abstract: The disclosure relates to a molecular crowding type electrolyte that comprises at least one type of water-miscible/soluble polymer which acts as molecular crowding agent, a salt and a water, The disclosure also relates to a battery comprising the molecular crowding type electrolyte, and a method of using the molecular crowding electrolyte in electrochemical system such as battery that comprises an anode, a cathode and the molecular crowding type electrolyte.

Abstract: An image device corresponding to depth information/panoramic image includes at least two image capturers. A first image capturer and a second image capturer of the at least two image capturers are used for capturing a plurality of first images and a plurality of second images, respectively. The first image capturer transmits the plurality of first images to an image processor, the second image capturer transmits the plurality of second images to the image processor, and the image processor generates depth information according to the plurality of first images, and generates panoramic images or panoramic videos according to the plurality of second images.

Abstract: The present application discloses a cork coding method and device, a cork tracing method and device, and an electronic device, wherein, the cork coding method comprises: acquiring an original image of a to-be-coded cork with an original character code; identifying the original character code in the original image; determining whether the original character code is matched with a character already inputted into a database; extracting an original texture feature of an to-be-coded cork from the original image, if the original character code is not matched with the character in the database; and establishing a one-to-one correspondence between the original texture feature and the original character code.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.