Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

Abstract: A semiconductor structure includes a substrate having a first region and a second region being adjacent each other; a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the patterned layer; and a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring includes a first width W1 and is spaced a first distance D1 from the first features, W1 being greater than D1.

Abstract: A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes first features in the first region. The second region is free of the patterned layer. The method further includes forming a material layer on the patterned layer and the substrate; forming a first guard ring disposed in the second region and surrounding the first features; forming a flowable-material (FM) layer over the material layer; forming a patterned resist layer over the FM layer, wherein the patterned resist layer includes a plurality of openings; and transferring the plurality of openings to the material layer.

Abstract: A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes first features in the first region. The second region is free of the patterned layer. The method further includes forming a material layer on the patterned layer and the substrate; forming a first guard ring disposed in the second region and surrounding the first features; forming a flowable-material (FM) layer over the material layer; forming a patterned resist layer over the FM layer, wherein the patterned resist layer includes a plurality of openings; and transferring the plurality of openings to the material layer.

Abstract: A light-emitting element, includes a substrate; a light-emitting stack formed on the substrate, including a triangular upper surface parallel to the substrate, having three sides and three vertexes; a first electrode formed on the light-emitting stack and located near a first vertex of the three vertexes of the triangular upper surface; and a second electrode formed on the light-emitting stack; including two second electrode pads respectively located near other two vertexes of the three vertexes; and a second electrode extending part extending from the second electrode pads, disposed along the three sides of the triangular upper surface.

Abstract: An aggregation of semiconductor devices comprises a first layer, a second layer adhered to the first layer, and a plurality of semiconductor devices arranged between the first layer and the second layer to form a shape, wherein the shape comprises a curve and a mark, and the first layer is flexible.

Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.

Abstract: Methods for identifying a test agent as a modulator of the active DNA demethylation activity of a DNA methyltransferase are disclosed. The method comprises: a) providing a methylated DNA; b) providing the DNA methyltransferase; c) allowing the methylated DNA to react with the DNA methyltransferase for a sufficient time to perform a demethylation reaction and generate a demethylated DNA product in the presence or absence of a test agent; d) analyzing the extent of demethylation; and d) comparing the extents of the demethylation in the presence and absence of the test agent, and thereby identify the test agent as a modulator of the DNA demethylation activity of the DNA methyltransferase.

Abstract: A light-emitting element, includes a substrate; a light-emitting stack formed on the substrate, including a triangular upper surface parallel to the substrate, having three sides and three vertexes; a first electrode formed on the light-emitting stack and located near a first vertex of the three vertexes of the triangular upper surface; and a second electrode formed on the light-emitting stack; including two second electrode pads respectively located near other two vertexes of the three vertexes; and a second electrode extending part extending from the second electrode pads, disposed along the three sides of the triangular upper surface.

Abstract: A light-emitting element, includes a substrate; a first light-emitting stack formed on the substrate, including a triangular upper surface parallel to the substrate, and wherein the triangular upper surface has three sides and three vertexes; a first electrode formed on the first light-emitting stack and located near a first side of the three sides of the triangular upper surface; and a second electrode formed on the first light-emitting stack; including a second electrode pad near a first vertex of the three vertexes; and a second electrode extending part extending from the second electrode pad in two directions, disposed along other two sides of the three sides to surround the first electrode and stopping at the first side to form an opening.

Abstract: An aggregation of semiconductor devices comprises a first layer, a second layer adhered to the first layer, and a plurality of semiconductor devices arranged between the first layer and the second layer to form a shape, wherein the shape comprises a curve and a mark, and the first layer is flexible.

Abstract: A method of manufacturing an aggregation of semiconductor devices comprising the steps of providing a first layer; sequentially addressing and adhering a plurality of semiconductor devices to the first layer to form a shape having a curve; providing a second layer; and adhering the second layer to the first layer.

Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.

Abstract: A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures.

Abstract: A light-emitting element, includes a substrate; a first light-emitting stack formed on the substrate, including a triangular upper surface parallel to the substrate, and wherein the triangular upper surface has three sides and three vertexes; a first electrode formed on the first light-emitting stack and located near a first side of the three sides of the triangular upper surface; and a second electrode formed on the first light-emitting stack; including a second electrode pad near a first vertex of the three vertexes; and a second electrode extending part extending from the second electrode pad in two directions, disposed along other two sides of the three sides to surround the first electrode and stopping at the first side to form an opening.

Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.

Abstract: A method of fabricating an optoelectronic device, comprises: providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a light emitting stack on the second major surface of the substrate; forming a supporting layer covering the light emitting stack; forming a plurality of first modified regions in the substrate by employing a first energy into the substrate after forming the supporting layer; and cleaving the substrate.

Abstract: A phase-locked pivot assembly includes a support component. A first shaft and a second shaft pivot relative to the support component. A first annular body is configured to rotate with the first shaft. The first annular body includes a first outer annular surface and a first sunken arc portion. A second annular body is configured to rotate with the second shaft and corresponds to the first annular body. The second annular body includes a second outer annular surface and a second sunken arc portion. The first sunken arc portion and the second outer annular surface are matched and selectively contact each other to lock the first shaft. The second sunken arc portion and the first outer annular surface are matched and selectively contact each other to lock the second shaft.

Abstract: Methods for identifying a test agent as a modulator of the active DNA demethylation activity of a DNA methyltransferase are disclosed. The method comprises: a) providing a methylated DNA; b) providing the DNA methyltransferase; c) allowing the methylated DNA to react with the DNA methyltransferase for a sufficient time to perform a demethylation reaction and generate a demethylated DNA product in the presence or absence of a test agent; d) analyzing the extent of demethylation; and d) comparing the extents of the demethylation in the presence and absence of the test agent, and thereby identify the test agent as a modulator of the DNA demethylation activity of the DNA methyltransferase.

Abstract: A method for manufacturing the image sensor device is provided. The method includes depositing a first dielectric layer over a back surface of a substrate, forming a ridge over the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, including filling in a space between two adjacent ridges. The method also includes removing the ridge to form a trench in the second dielectric layer and forming a metal grid in the trench.