Abstract: An improved hoop support for semiconductor wafers reduces contamination of the wafer during edge beveling operations through the use of support pins that make only line contact with the wafer. The support pins are spaced around the periphery of the hoop and possess a triangular cross section. Two intersecting sides of the pins form an edge that defines the line contact with the wafer. These intersecting sides are preferably inclined relative to the wafer at an angle of between 60 and 80 degrees.

Abstract: An apparatus and a method for removing coating layers from the top of alignment marks on a wafer are described. The apparatus includes a cleaning chamber that is a cavity and a lid member suspended in the cavity, a wafer chuck that is rotatably mounted in the lid member for holding a wafer in an upside down position such that the alignment marks are facing downwardly, and at least two solvent dispensing arms mounted in an outer peripheral area of the lid member that are immediately adjacent to the chuck for dispensing a flow of solvent upwardly toward the active surface of the wafer when the wafer is held in a stationary position, each of the at least two solvent dispensing arms are positioned corresponding to a position of one of the alignment marks.

Abstract: An improved hoop support for semiconductor wafers reduces contamination of the wafer during edge beveling operations through the use of support pins that make only line contact with the wafer. The support pins are spaced around the periphery of the hoop and possess a triangular cross section. Two intersecting sides of the pins form an edge that defines the line contact with the wafer. These intersecting sides are preferably inclined relative to the wafer at an angle of between 60 and 80 degrees.

Abstract: An apparatus and a method for removing coating layers from the top of alignment marks on a wafer are described. The apparatus includes a cleaning chamber that is a cavity and a lid member suspended in the cavity, a wafer chuck that is rotatably mounted in the lid member for holding a wafer in an upside down position such that the alignment marks are facing downwardly, and at least two solvent dispensing arms mounted in an outer peripheral area of the lid member that are immediately adjacent to the chuck for dispensing a flow of solvent upwardly toward the active surface of the wafer when the wafer is held in a stationary position, each of the at least two solvent dispensing arms are positioned corresponding to a position of one of the alignment marks.

Abstract: A process for preparing a surface of a lower level metal structure, exposed at the bottom of a sub-micron diameter opening, to allow a low resistance interface to be obtained when overlaid with an upper level metal structure, has been developed. A disposable, capping insulator layer is first deposited on the composite insulator layer in which the sub-micron diameter opening will be defined in, to protect underlying components of the composite insulator from a subsequent metal pre-metal procedure. After anisotropically defining the sub-micron diameter opening in the capping insulator, and composite insulator layers, and after removal of the defining photoresist shape, an argon sputtering procedure is used to remove native oxide from the surface of the lower level metal structure. In addition to native oxide removal the argon sputtering procedure, featuring a negative DC bias applied to the substrate, also removes the capping insulator layer from the top surface of the composite insulator layer.

Abstract: A method of forming a PE-silane oxide layer with a greatly reduced particle count is described. A semiconductor substrate is provided over which a silicon oxide film is to be formed. The silicon oxide film is formed by the steps of: 1) pre-flowing a non-silane gas into a deposition chamber for at least two seconds whereby the pre-flowing step prevents formation of particles on the silicon oxide film, and 2) thereafter depositing a silicon oxide film by chemical vapor deposition by flowing a silane gas into the deposition chamber to complete formation of a silicon oxide film using plasma-enhanced chemical vapor deposition in the fabrication of an integrated circuit.