Abstract: A method for manufacturing the image sensor device is provided. The method includes depositing a first dielectric layer over a back surface of a substrate, forming a ridge over the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, including filling in a space between two adjacent ridges. The method also includes removing the ridge to form a trench in the second dielectric layer and forming a metal grid in the trench.

Abstract: A method of manufacturing an aggregation of semiconductor devices comprising the steps of providing a first layer; sequentially addressing and adhering a plurality of semiconductor devices to the first layer to form a shape having a curve; providing a second layer; and adhering the second layer to the first layer.

Abstract: A method of fabricating an optoelectronic device, comprising: providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a light emitting stack on the second major surface of the substrate; forming a supporting layer covering the light emitting stack; forming a plurality of first modified regions in the substrate by employing a first energy into the substrate after forming the supporting layer; and cleaving the substrate.

Abstract: A method of chip sorting comprises providing a chip holder having a first surface; providing multiple chips on the first surface; providing a chip receiver having a second surface, wherein the second surface faces the first surface; attaching the multiple chips to the second surface; decreasing an adhesion between the multiple chips and the first surface; and separating the multiple chips from the first surface after the step of decreasing the adhesion between the multiple chips and the first surface.

Abstract: The present invention is related to a phase-locked pivot assembly, which includes a support component. A first shaft and a second shaft pivot to the support component. A first annular body is configured to rotate with the first shaft. The first annular body includes a first outer annular surface and a first sunken arc portion. A second annular body is configured to rotate with the second shaft and corresponds to the first annular body. The second annular body includes a second outer annular surface and a second sunken arc portion. The first sunken arc portion and the second outer annular surface are matched and selectively contact to each other to lock the first shaft. The second sunken arc portion and the first outer annular surface are matched and selectively contact to each other to lock the second shaft.

Abstract: An aggregation of semiconductor devices, comprising: a first layer comprising a first surface and a second surface; a second layer comprising a first region and a second region; and a plurality of semiconductor devices disposed between the first layer and the second region wherein a shape of the second region comprises a curve and a mark.

Abstract: A method of fabricating an optoelectronic device, comprising: providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a light emitting stack on the second major surface of the substrate; forming a supporting layer covering the light emitting stack; forming a plurality of first modified regions in the substrate by employing a first energy into the substrate, wherein the supporting layer is formed before forming the plurality of first modified regions; forming an oxide layer on the first major surface of the substrate; and cleaving the substrate along the plurality of first modified regions.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate having two different topography areas adjacent to each other. A step-forming material (SFM) is deposited over the substrate. A patterned SFM is formed in the low topography area of the two areas. The formation of the patterned SFM provides a fairly planar surface across over the substrate.

Abstract: An integrated circuit structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The integrated circuit structure further includes a conductive wiring in the dielectric layer. The integrated circuit structure also includes a first metallic capping layer over the conductive wiring and a second metallic capping layer over the first metallic capping layer. The second metallic capping layer has a width substantially the same as a width of the first metallic capping layer.

Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.

Abstract: A method of chip sorting comprises providing a chip holder having a first surface; providing multiple chips on the first surface; providing a chip receiver having a second surface, wherein the second surface faces the first surface; attaching the multiple chips to the second surface; decreasing an adhesion between the multiple chips and the first surface; and separating the multiple chips from the first surface after the step of decreasing the adhesion between the multiple chips and the first surface.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.

Abstract: A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures.

Abstract: A chip sorting apparatus comprising a chip holder comprising a first surface and an second surface opposite to the first surface; a wafer comprising a first chip disposed on a first position of the first surface; a first chip receiver comprising a third surface and an fourth surface opposite to the third surface, wherein the third surface is opposite to the first surface; a pressurization device making the first chip and the third surface of the first chip receiver adhered to each other through pressuring the second surface at where corresponding to the first position; and a separator decreasing the adhesion between the first chip and the first surface.

Abstract: Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate having two different topography areas adjacent to each other. A step-forming material (SFM) is deposited over the substrate. A patterned SFM is formed in the low topography area of the two areas. The formation of the patterned SFM provides a fairly planar surface across over the substrate.

Abstract: An illumination apparatus is disclosed in the invention. The illumination apparatus includes a cavity with a diffusion surface, a light source, a light-spreading device, and at least one optically-conditioning surface with a wave-like array formed thereon. The light-spreading device and the optically-conditioning surface spread the light generated by the light source. The light-spreading device includes a wing-shaped protrusion part, a light incident surface, a recess located away from the light incident surface, and an optically-conditioning surface including a wave-like array, wherein the wave-like array has a wavefront direction.

Abstract: An aggregation of semiconductor devices, comprising: a first layer comprising a first surface and a second surface; a second layer comprising a first region and a second region; and a plurality of semiconductor devices disposed between the first layer and the second region wherein a shape of the second region comprises a curve and a mark.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.

Abstract: A method of fabricating an optoelectronic device, comprising: providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a light emitting stack on the second major surface of the substrate; forming an supporting layer covering the light emitting stack; forming a plurality of first modified regions in the substrate by employing an first energy into the substrate; forming an oxide layer on the first major surface of the substrate; and cleaving the substrate along the plurality of the first modified regions.