Abstract: An embodiment of the present disclosure discloses a phosphor material and a manufacturing method thereof. The general composition of the phosphor material is A2-xMO4:Eux, wherein A includes a single element or at least two elements selected from the group consisting of Ca, Sr, and Ba, M is Si, Ge or combination thereof, wherein x is greater than 0.01 and 2-x>0. The phosphor material can be excited by a first excitation wavelength and emit a first emission spectrum and, excited by a second excitation wavelength and emit a second emission spectrum. The first excitation wavelength is different from the second excitation wavelength, and the first emission spectrum is different from the second emission spectrum.

Abstract: The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface, a plurality of sensor elements disposed at the front surface of the substrate. Each of the plurality of sensor elements is operable to sense radiation projected towards the back surface of the substrate. The image sensor also includes a high-k dielectric grid disposed over the back surface of the substrate. The high-k dielectric grid has a high-k dielectric trench and sidewalls. The image sensor also includes a color filter and a microlens disposed over the high-k dielectric grid.

Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.

Abstract: A phosphor, having a general formula of K2[Si1-xGex]yF6:Mn1-y4+. The phosphor is excited to emit a light having a first main emission peak with a first maximum emission intensity and a first dominant wavelength, wherein a relative emission intensity S of the light of the phosphor is constantly greater than 85% across an temperature of the phosphor between 300 K and 470 K during operation, wherein S=(IT/IRT)*100%, IRT and IT are the first maximum emission intensity when the temperature of the phosphor is at 300 K and T during operation respectively, and 300 K<T?470K.

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.

Abstract: A semiconductor device includes a substrate, at least one layer, a metal adhesive, and a metal structure. The layer is disposed on the substrate. The layer has an opening, and the opening has a bottom surface and at least one sidewall. The metal adhesive is disposed on the bottom surface of the opening while leaving at least a portion of the sidewall of the opening exposed. The metal structure is disposed in the opening and on the metal adhesive.

Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

Abstract: The present invention provides a phosphor represented by the following formula: K2[Ge1-xF6]:Mnx4+, wherein 0<x<0.2. The phosphor has a hexagonal phase of a P63mc space group. The present invention also provides a method for fabricating the above phosphor. The present invention further provides a light-emitting device and a backlight module employing the same.

Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.

Abstract: Buffer layers on gates and methods of forming such are described. According to a method embodiment, a gate structure is formed. The gate structure includes a gate dielectric over a substrate, a work function tuning layer over the gate dielectric, and a metal-containing material over the work function tuning layer. A buffer layer is formed on the metal-containing material. A dielectric material is formed on the buffer layer. According to a structure embodiment, a gate structure includes a high-k gate dielectric and a metal gate electrode. A buffer layer is on the metal gate electrode. A dielectric cap is on the buffer layer. An inter-layer dielectric is over the substrate and around the gate structure. A top surface of the inter-layer dielectric is co-planar with a top surface of the dielectric cap.

Abstract: An LED structure is applied to a backlight source to set a white light of a backlight module at a standard D65 position of the CIE1931 chromaticity coordinates and used together with a display module. A red phosphor for emitting a red light, a yellow phosphor for emitting a yellow light, and a blue light LED chip are provided. The mixing ratio of the red phosphor to the yellow phosphor is controlled within a range of (2.33?1):1, so that the original LED white light falls within a region enclosed by ccy?1.8*ccx?0.12, ccy?1.8*ccx?0.336, ccy?0.33 and ccy?0.15 of the CIE1931 coordinates. Since the red phosphor does not absorb or convert yellow light, the brightness loss of the yellow light that excites the yellow phosphor is minimized. A color filter may be installed to achieve better NTSC effect and luminous efficacy.

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate; wherein the gate stack includes a high k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer, wherein the gate stack has a convex top surface.

Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.