Patents by Inventor Chun-Chen Chen
Chun-Chen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12254260Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.Type: GrantFiled: July 28, 2023Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Hsiung Chen, Chun-Chen Chen, Shao-huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Ren-Zheng Liao, Meng-Xiang Lee
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Patent number: 12224662Abstract: An LLC resonant converter with variable turns ratio includes a switching circuit coupled to a DC input voltage for converting the DC voltage into switching signal, a resonant tank coupled to the switching circuit and configured to receive the switching signal to provide a primary current, a transformer circuit coupled to the resonant tank. The transformer circuit includes a plurality of separated transformers, each has a primary side winding and a side secondary side winding, where individual transformer has different turns of primary side winding, which can be dynamically selected to couple with the primary side winding of other transformers in series or in parallel to form a dynamically changing equivalent primary side winding, so that the turns ratio in the transformer circuit can be dynamically changed accordingly.Type: GrantFiled: October 15, 2022Date of Patent: February 11, 2025Assignee: PHIHONG TECHNOLOGY CO., LTD.Inventors: Chun-Chen Chen, Jian-Hsieng Lee, Yao-Chun Tung
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Patent number: 12224481Abstract: A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.Type: GrantFiled: March 7, 2023Date of Patent: February 11, 2025Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Lin Ho, Chih-Cheng Lee, Chun Chen Chen, Yuanhao Yu
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Patent number: 12199505Abstract: An LLC resonant converter with variable resonant tank includes a switching circuit for converting a DC voltage into switching signal, a variable resonant tank coupled to the switching circuit for receiving the switching signal to provide a primary current, a transformer circuit having a primary and a secondary side winding, and a rectifying/filtering circuit to rectifying and filtering a secondary current. The variable resonant tank is coupled between the switching circuit and the transformer circuit, which includes a variable resonant inductor, a magnetizing inductance and a resonant capacitor coupled in series for dynamically adjusting the gain curve of the LLC resonant converter according to the demand of the output current.Type: GrantFiled: October 15, 2022Date of Patent: January 14, 2025Assignee: PHIHONG TECHNOLOGY CO., LTD.Inventors: Chun-Chen Chen, Jian-Hsieng Lee, Yao-Chun Tung
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Publication number: 20240421103Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.Type: ApplicationFiled: August 27, 2024Publication date: December 19, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chia Hsiu HUANG, Chun Chen CHEN, Wei Chih CHO, Shao-Lun YANG
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Publication number: 20240387373Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
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Publication number: 20240354487Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.Type: ApplicationFiled: July 2, 2024Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fong-yuan CHANG, Chun-Chen CHEN, Sheng-Hsiung CHEN, Ting-Wei CHIANG, Chung-Te LIN, Jung-Chan YANG, Lee-Chung LU, Po-Hsiang HUANG
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Patent number: 12113454Abstract: An LLC resonant converter includes a switching circuit for converting a DC voltage into switching signal, a resonant tank coupled to the switching circuit to receive the switching signal and to provide a primary current, a transformer circuit coupled to the resonant tank. The transformer circuit includes a plurality of separated transformers, each has a primary side and a secondary side windings disposed on the PCB, where the primary side winding of each transformer can be selected to couple in series or in parallel with the primary side winding of other transformers to form a dynamically varied equivalent primary side winding, maintaining the turns ratio to fine-tune the resonant tank. The gain curve of the LLC converter can be adjusted by electrically coupling an external excitation inductor, a resonant capacitor or a resonant inductor to the resonant tank, according to the demand of output current.Type: GrantFiled: October 15, 2022Date of Patent: October 8, 2024Assignee: PHIHONG TECHNOLOGY CO., LTD.Inventors: Chun-Chen Chen, Jian-Hsieng Lee, Yao-Chun Tung
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Patent number: 12087690Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: GrantFiled: July 29, 2022Date of Patent: September 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
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Patent number: 12074118Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.Type: GrantFiled: June 13, 2023Date of Patent: August 27, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chia Hsiu Huang, Chun Chen Chen, Wei Chih Cho, Shao-Lun Yang
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Patent number: 12056432Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.Type: GrantFiled: April 13, 2023Date of Patent: August 6, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chun-Chen Chen, Sheng-Hsiung Chen, Ting-Wei Chiang, Chung-Te Lin, Jung-Chan Yang, Lee-Chung Lu, Po-Hsiang Huang
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Publication number: 20240203997Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.Type: ApplicationFiled: March 4, 2024Publication date: June 20, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
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Publication number: 20240146176Abstract: A method of controlling phase shift pulse width modulation of a power converter, the method includes a step of obtaining sampling signals of an output voltage and current of the power converter. Then, a digital signal processor is used to calculate an output power of the power converter. Next, a comparator is used to compare the output power of the power converter with a reference power. When the output power is less than the reference power, the modulation control of the switch of the power converter enters into hard-switching mode, and when the output power is greater than the reference power, the modulation control of the switch of the power converter enters into soft-switching mode.Type: ApplicationFiled: November 24, 2022Publication date: May 2, 2024Inventors: Chun-Chen Chen, Jian-Hsieng Lee, Feng-Yi Lin
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Patent number: 11935894Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.Type: GrantFiled: November 4, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
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Publication number: 20240088899Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: SHAO-HUAN WANG, CHUN-CHEN CHEN, SHENG-HSIUNG CHEN, KUO-NAN YANG
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Publication number: 20240088001Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.Type: ApplicationFiled: September 19, 2023Publication date: March 14, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Lin HO, Chih-Cheng LEE, Chun Chen CHEN, Cheng Yuan CHEN
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Publication number: 20240079952Abstract: An LLC resonant converter with variable turns ratio includes a switching circuit coupled to a DC input voltage for converting the DC voltage into switching signal, a resonant tank coupled to the switching circuit and configured to receive the switching signal to provide a primary current, a transformer circuit coupled to the resonant tank. The transformer circuit includes a plurality of separated transformers, each has a primary side winding and a side secondary side winding, where individual transformer has different turns of primary side winding, which can be dynamically selected to couple with the primary side winding of other transformers in series or in parallel to form a dynamically changing equivalent primary side winding, so that the turns ratio in the transformer circuit can be dynamically changed accordingly.Type: ApplicationFiled: October 15, 2022Publication date: March 7, 2024Inventors: Chun-Chen Chen, Jian-Hsieng Lee, Yao-Chun Tung
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Publication number: 20240079953Abstract: An LLC resonant converter with variable resonant tank includes a switching circuit for converting a DC voltage into switching signal, a variable resonant tank coupled to the switching circuit for receiving the switching signal to provide a primary current, a transformer circuit having a primary and a secondary side winding, and a rectifying/filtering circuit to rectifying and filtering a secondary current. The variable resonant tank is coupled between the switching circuit and the transformer circuit, which includes a variable resonant inductor, a magnetizing inductance and a resonant capacitor coupled in series for dynamically adjusting the gain curve of the LLC resonant converter according to the demand of the output current.Type: ApplicationFiled: October 15, 2022Publication date: March 7, 2024Inventors: Chun-Chen Chen, Yao-Chun Tung, Jian-Hsieng Lee
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Publication number: 20240079965Abstract: An LLC resonant converter includes a switching circuit for converting a DC voltage into switching signal, a resonant tank coupled to the switching circuit to receive the switching signal and to provide a primary current, a transformer circuit coupled to the resonant tank. The transformer circuit includes a plurality of separated transformers, each has a primary side and a secondary side windings disposed on the PCB, where the primary side winding of each transformer can be selected to couple in series or in parallel with the primary side winding of other transformers to form a dynamically varied equivalent primary side winding, maintaining the turns ratio to fine-tune the resonant tank. The gain curve of the LLC converter can be adjusted by electrically coupling an external excitation inductor, a resonant capacitor or a resonant inductor to the resonant tank, according to the demand of output current.Type: ApplicationFiled: October 15, 2022Publication date: March 7, 2024Inventors: Chun-Chen Chen, Jian-Hsieng Lee, Yao-Chun Tung
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Publication number: 20240020451Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.Type: ApplicationFiled: July 28, 2023Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Hsiung Chen, Chun-Chen Chen, Shao-huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Ren-Zheng Liao, Meng-Xiang Lee