Patents by Inventor Chun-Chen Chen

Chun-Chen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230211451
    Abstract: An intelligent analysis system for measuring signals of polishing pad surface, a method and a computer readable medium thereof are provided. The intelligent analysis system includes a measurement signal capturing device and a measurement signal analysis device signally-connected to each other. After the measurement signal capturing device obtains the measurement signal of the measured polishing pad, an artificial intelligence model of the measurement signal analysis device is trained to classify the measurement signal to remove the interference caused by a water film on the polishing pad to obtain a better measurement signal, such that the intelligent analysis system can solve the problems of time-consuming, laborious and misjudgment caused by the classification of the measurement signal by the conventional technology.
    Type: Application
    Filed: December 5, 2022
    Publication date: July 6, 2023
    Inventors: Hsien-Ming LEE, Chun-Chen CHEN, Ching-Tang HSUEH
  • Patent number: 11682660
    Abstract: The present disclosure provides a semiconductor structure including a first substrate having a first surface, a first semiconductor device package disposed on the first surface of the first substrate, and a second semiconductor device package disposed on the first surface of the first substrate. The first semiconductor device package and the second semiconductor device package have a first signal transmission path through the first substrate and a second signal transmission path insulated from the first substrate. The present disclosure also provides an electronic device.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: June 20, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuanhao Yu, Chun Chen Chen, Shang Chien Chen
  • Patent number: 11676912
    Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 13, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia Hsiu Huang, Chun Chen Chen, Wei Chih Cho, Shao-Lun Yang
  • Patent number: 11658102
    Abstract: A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than ?20 dB.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: May 23, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuanhao Yu, Cheng Yuan Chen, Chun Chen Chen, Jiming Li, Chien-Wen Tu
  • Publication number: 20230145588
    Abstract: A semiconductor package includes a substrate, a preformed feeding element, a preformed shielding element, and an encapsulant. The preformed feeding element is disposed on the substrate and the preformed feeding element is disposed on the substrate and adjacent to the preformed feeding element. The encapsulant encapsulates the preformed feeding element and the preformed shielding element.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 11, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng Yuan CHEN, Jiming LI, Chun Chen CHEN, Yuanhao YU
  • Patent number: 11637098
    Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Lee-Chung Lu, Po-Hsiang Huang, Chun-Chen Chen, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Chen, Jung-Chan Yang
  • Patent number: 11633834
    Abstract: A method for repairing a polishing pad in real time includes a trimming step, a detection step, and a reconstruction and analysis step. A surface morphology of the polishing pad is reconstructed through detection, and analysis is performed according to the reconstruction, to ensure that a surface of the polishing pad can recover its function after the surface of the polishing pad is trimmed, so that the polishing pad can be used effectively to reduce costs.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: April 25, 2023
    Assignee: TA LIANG TECHNOLOGY CO., LTD.
    Inventors: Chao-Chang Chen, Jian-Shian Lin, Chun-Chen Chen, Jen-Chien Li, Hsien-Ming Lee, Ching-Tang Hsueh
  • Patent number: 11600901
    Abstract: A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 7, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee, Chun Chen Chen, Yuanhao Yu
  • Patent number: 11594360
    Abstract: The present invention provides an electromagnetic apparatus with heat sink structure, comprising: metal housing, the metal housing further comprises the upper housing and the lower housing to fix the components of the electromagnetic apparatus and store the energy of the electromagnetic apparatus during operation; the electrical coil is mounted on the coil shelf and is provided with numbers of primary windings and secondary windings; the heat conductive tube is arranged in the gap of the windings for conducting the heat generated by the electrical coil to the outside of the electromagnetic apparatus. Furthermore, the conducting wire is electrically coupled to the electrical coil and transmits the input voltage and output voltage during the operation of electromagnetic apparatus.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: February 28, 2023
    Assignee: PHIHONG TECHNOLOGY CO., LTD.
    Inventors: Chun-Chen Chen, Jian-Hsieng Lee, Feng-Yi Lin, Pang-Chuan Chen
  • Publication number: 20230057672
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Application
    Filed: November 4, 2022
    Publication date: February 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan CHANG, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jul Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Patent number: 11551066
    Abstract: A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 10, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua Chen, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Chun-Hung Lai, Juin-Ming Lu
  • Patent number: 11552026
    Abstract: A semiconductor package includes a substrate, a preformed feeding element, a preformed shielding element, and an encapsulant. The preformed feeding element is disposed on the substrate and the preformed feeding element is disposed on the substrate and adjacent to the preformed feeding element. The encapsulant encapsulates the preformed feeding element and the preformed shielding element.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: January 10, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng Yuan Chen, Jiming Li, Chun Chen Chen, Yuanhao Yu
  • Publication number: 20220379433
    Abstract: Provided is a dressing device for a carrier. The dressing device comprises a dresser, a swing arm, a base and at least one damper. A first end and a second end of the swing arm are coupled to the dresser and the base, respectively, and the at least one damper is disposed inside the swing arm. Any axial vibration of the dresser or the swing arm during dressing for the carrier can be compensated or attenuated by the damper in an active manner properly, so as to make the surface of the carrier flatter and more uniform, which not only improves a removal rate of material and a polishing result of the surface in the subsequent chemical mechanical planarization process, but also prolongs the service life of the carrier. The present disclosure further relates to a polishing system for dressing the carrier by using the said dressing device.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 1, 2022
    Inventors: Chao-Chang Chen, Jen-Chieh Li, Cheng-Hsi Chuang, Shih-Chung Hsu, Yu-Tung Tsai, Hsien-Ming Lee, Chun-Chen Chen, Ching-Tang Hsueh
  • Publication number: 20220367358
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20220358277
    Abstract: A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Shao-Huan WANG, Sheng-Hsiung CHEN, Wen-Hao CHEN, Chun-Chen CHEN, Hung-Chih OU
  • Patent number: 11495619
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Patent number: 11491608
    Abstract: Disclosed are a detection method and a detection apparatus for a polishing pad of a chemical mechanical polishing device, particularly a detection method and a detection apparatus for detecting a surface of a polishing pad dynamically. An isolation region isolated by a gas to expose the polishing pad is formed by the detecting device, and a detection is performed on the isolation region, such that the chemical mechanical polishing device is capable of detecting the polishing pad without interrupting a manufacturing process and the detection results with more accurate can be achieved. Thereby, the polishing pad can be repaired and replaced more timely.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: November 8, 2022
    Assignee: Ta Liang Technology Co., Ltd.
    Inventors: Hsien-Ming Lee, Chun-Chen Chen, Ching-Tang Hsueh, Po-Ching Huang
  • Patent number: 11462467
    Abstract: A lead frame includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion and an outer lead portion connecting to the inner lead portion. The inner lead portion is adjacent to and spaced apart from the die paddle. A bottom surface of the inner lead portion is higher than a bottom surface of the outer lead portion. The bottom surface of the inner lead portion includes one or more supporting members disposed thereon. The one or more supporting members have a convex surface facing away from the inner lead portion.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia Hsiu Huang, Chun Chen Chen, Wei Chih Cho, Shao-Lun Yang, Yu-Shun Hsieh
  • Patent number: 11447105
    Abstract: The present disclosure relates to methods and associated systems for operating a battery exchange station. The present technology (1) receives battery information from a memory attached to each of a plurality of exchangeable batteries positioned in the battery exchange station; (2) receives a battery demand prediction associated with the battery exchange station; and (3) identifying one or more uninterruptible-power-supply (UPS) batteries from the plurality of exchangeable batteries at least partially based in part on the battery demand prediction and individual state of charges (SoCs) of the plurality of exchangeable batteries.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: September 20, 2022
    Assignee: Gogoro Inc.
    Inventors: I-Fen Shih, Yun-Chun Lai, Chien-Chung Chen, Chun-Chen Chen, Yu-Lin Wu
  • Patent number: 11449656
    Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou