Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.

Abstract: A system and a method for uniformed surface measurement are provided, in which a sensor is provided to perform measurements on a carrier in a polishing machine, and a measuring trajectory of the sensor on the carrier is adjusted by controlling the pivoting of a sensor carrier carrying the sensor and the rotation of a rotating platform in the polishing machine in order to achieve uniformed surface measurements of the carrier and real-time constructions of the surface topography. This allows the polishing state of the carrier to be monitored in real time, thereby improving the efficiency of the polishing process. A sensing apparatus for uniformed surface measurement is also provided.

Abstract: The present disclosure provides a semiconductor structure including a first substrate having a first surface, a first semiconductor device package disposed on the first surface of the first substrate, and a second semiconductor device package disposed on the first surface of the first substrate. The first semiconductor device package and the second semiconductor device package have a first signal transmission path through the first substrate and a second signal transmission path insulated from the first substrate. The present disclosure also provides an electronic device.

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Abstract: A hardware together with a software are used to implement a control pilot (CP) status detection for protecting a DC charging pile when errors happens, such as short circuit or open circuit, at CP point. The circuit for detecting the abnormality of the CP point includes a detection circuit, which is coupled to a CP signal generating circuit of the charging pile to provide an abnormal state detection when an electrical vehicle is electrically connected to the DC charging pile, and output the detected CP signal to a control circuit. It includes a DC voltage converter that converts a DC input voltage into two DC output reference voltage levels, a rectifier circuit to filter out the negative potential of the CP signal generating by the CP signal generating circuit, and a CP signal isolation circuit, connected to the rectifier circuit to provide isolated CP signals to the control circuit.

Abstract: A lead frame includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion and an outer lead portion connecting to the inner lead portion. The inner lead portion is adjacent to and spaced apart from the die paddle. A bottom surface of the inner lead portion is higher than a bottom surface of the outer lead portion. The bottom surface of the inner lead portion includes one or more supporting members disposed thereon. The one or more supporting members have a convex surface facing away from the inner lead portion.

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a first substrate, a second substrate, and a barrier structure. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface facing the second surface of the first substrate. The first substrate electrically bonds to the second substrate through a conductive terminal disposed between the second surface of the first substrate and the first surface of the second substrate. The barrier structure is disposed adjacent to the first surface of the first substrate.

Abstract: A semiconductor device package and a method for manufacturing the same are provided. The semiconductor device package includes a circuit layer and an antenna module. The circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface. The lateral surface extends between the first surface and the second surface. The circuit layer has an interconnection structure. The antenna module has an antenna pattern layer and is disposed on the first surface of the circuit layer. The lateral surface of the circuit layer is substantially coplanar with a lateral surface of the antenna module.

Abstract: A system and a method for uniformed surface measurement are provided, in which a sensor is provided to perform measurements on a carrier in a polishing machine, and a measuring trajectory of the sensor on the carrier is adjusted by controlling the pivoting of a sensor carrier carrying the sensor and the rotation of a rotating platform in the polishing machine in order to achieve uniformed surface measurements of the carrier and real-time constructions of the surface topography. This allows the polishing state of the carrier to be monitored in real time, thereby improving the efficiency of the polishing process. A sensing apparatus for uniformed surface measurement is also provided.

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Abstract: A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.

Abstract: The present invention provides an electromagnetic apparatus with heat sink structure, comprising: metal housing, the metal housing further comprises the upper housing and the lower housing to fix the components of the electromagnetic apparatus and store the energy of the electromagnetic apparatus during operation; the electrical coil is mounted on the coil shelf and is provided with numbers of primary windings and secondary windings; the heat conductive tube is arranged in the gap of the windings for conducting the heat generated by the electrical coil to the outside of the electromagnetic apparatus. Furthermore, the conducting wire is electrically coupled to the electrical coil and transmits the input voltage and output voltage during the operation of electromagnetic apparatus.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: A hardware together with a software are used to implement a control pilot (CP) status detection for protecting a DC charging pile when errors happens, such as short circuit or open circuit, at CP point. The circuit for detecting the abnormality of the CP point includes a detection circuit, which is coupled to a CP signal generating circuit of the charging pile to provide an abnormal state detection when an electrical vehicle is electrically connected to the DC charging pile, and output the detected CP signal to a control circuit. It includes a DC voltage converter that converts a DC input voltage into two DC output reference voltage levels, a rectifier circuit to filter out the negative potential of the CP signal generating by the CP signal generating circuit, and a CP signal isolation circuit, connected to the rectifier circuit to provide isolated CP signals to the control circuit.

Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

Abstract: A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than ?20 dB.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: Disclosed are a detection method and a detection apparatus for a polishing pad of a chemical mechanical polishing device, particularly a detection method and a detection apparatus for detecting a surface of a polishing pad dynamically. An isolation region isolated by a gas to expose the polishing pad is formed by the detecting device, and a detection is performed on the isolation region, such that the chemical mechanical polishing device is capable of detecting the polishing pad without interrupting a manufacturing process and the detection results with more accurate can be achieved. Thereby, the polishing pad can be repaired and replaced more timely.

Abstract: A semiconductor device package and a method for manufacturing the same are provided. The semiconductor device package includes a circuit layer and an antenna module. The circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface. The lateral surface extends between the first surface and the second surface. The circuit layer has an interconnection structure. The antenna module has an antenna pattern layer and is disposed on the first surface of the circuit layer. The lateral surface of the circuit layer is substantially coplanar with a lateral surface of the antenna module.