Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253893
    Abstract: A system and a method for automatically adjusting a beam direction of a reflector are provided. The system includes: a reflector for reflecting, refracting, or transmitting incident waves of network signals to a specified area; a database, storing optimized setting combinations for specified areas that include an altitude of the reflector and angles thereof with respect to the specified area, making signals of the specified area have maximum intensity; a communication module, receiving a trigger signal; a computing and processing module, retrieving from the optimized setting combination for the specified area according to the area name of the trigger signal; and a control module, adjusting the altitude and angles of the reflector according to the optimized setting combination. The disclosure can automatically detect a specified area needing network service and automatically adjust the reflector for signal intensity enhancement.
    Type: Application
    Filed: April 25, 2024
    Publication date: August 7, 2025
    Inventors: CHUN-CHIEH KUO, HUA-PEI CHIANG, CHYI-DAR JANG, CHI-HUNG LIN, TSUNG-JEN WANG, CHE-YU LIAO, CHI-EN CHIEN, HAO CHEN
  • Patent number: 12382693
    Abstract: Some implementations described herein provide a nanostructure transistor including inner spacers between a gate structure and a source/drain region. The inner spacers, formed in cavities at end regions of sacrificial nanosheets during fabrication of the nanostructure transistor, include concave-regions that face the source/drain region. Formation techniques include forming the sacrificial nanosheets and inner spacers to include certain geometric and/or dimensional properties, such that a likelihood of defects and/or voids within the inner spacers and/or the gate structure are reduced.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: August 5, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Wei Chang, Shahaji B. More, Chi-Yu Chou, Chun Chieh Wang, Yueh-Ching Pai
  • Publication number: 20250248046
    Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer and a first alignment layer. The first alignment layer is disposed between the first electrode layer and the ferroelectric layer, and the ferroelectric layer and the first alignment layer have the same crystal lattice orientation. In some embodiments, a material of the first alignment layer has a band gap smaller than 50 meV.
    Type: Application
    Filed: March 20, 2025
    Publication date: July 31, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Qing Shi, Bo-Feng Young, Yu-Chuan Shih, Sai-Hooi Yeong, Blanka Magyari-Kope, Ying-Chih Chen, Tzer-Min Shen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12376347
    Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chang Chiang, Yu-Chuan Shih, Chun-Chieh Lu, Po-Ting Lin, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20250241015
    Abstract: Oxide semiconductor ferroelectric field effect transistors (OS-FeFETs) and method of forming the same are provide. A device disclosed herein includes an electrode in a first dielectric layer, a ferroelectric layer over the electrode and the first dielectric layer, a high-k dielectric layer over the ferroelectric layer, an oxide semiconductor layer over the high-k dielectric layer, a second dielectric layer over the oxide semiconductor layer and the high-k dielectric layer, and a first contact feature and a second contact feature extending through the second dielectric layer to contact the oxide semiconductor layer.
    Type: Application
    Filed: March 28, 2024
    Publication date: July 24, 2025
    Inventors: Chun-Chieh Lu, Yu-Chuan Shih, Yu-Ming Lin
  • Publication number: 20250241064
    Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.
    Type: Application
    Filed: April 9, 2025
    Publication date: July 24, 2025
    Inventors: Chun-Chieh LU, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Han-Jong Chia
  • Patent number: 12361911
    Abstract: A control device is configured to control a display panel according to a trigger signal transmitted from an input device to a host. The control device includes a connector unit and a signal capture unit. The connector unit is configured to receive the trigger signal, and transmit the same to the host. The signal capture unit is configured to capture the trigger signal, and control the display panel according to the trigger signal while the connector unit is transmitting the trigger signal to the host.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: July 15, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Cian-Rou Wu, Cheng Yueh Chen, Chun-Chieh Chan
  • Publication number: 20250227934
    Abstract: A method is provided. The method includes applying a first pulse to a ferroelectric memory device, measuring a memory window metric of the ferroelectric memory device, and applying a second pulse to the ferroelectric memory device. The first pulse may have a first voltage magnitude. The second pulse may have a second voltage magnitude. The second voltage magnitude may be determined based at least in part on the measured memory window metric.
    Type: Application
    Filed: January 8, 2024
    Publication date: July 10, 2025
    Inventors: YU-CHUAN SHIH, YU-KAI CHANG, PEI-CHUN LIAO, HUAI-YING HUANG, CHUN-CHIEH LU, YU-MING LIN
  • Patent number: 12355143
    Abstract: A signal sensing device includes a body and two signal sensing elements disposed in the body. An insulating layer is sandwiched between the two signal sensing elements. Each of the two signal sensing elements incudes a signal transmission section and a signal sensing section in electrical connection with the signal transmission section. The signal transmission sections are planar antennae parallel to each other and each having an antenna shape of meander-line type. The antenna shape of each transmission section has a vertical projection on a plane parallel to each signal transmission section. The vertical projections of the antenna shapes do not overlap completely. When a portion of the body forms a surrounding portion which surrounds a to-be-sensed target, a portion or an entirety of each signal sensing section is located on the surrounding portion.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: July 8, 2025
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Shu-Hung Huang, Chun-Chieh Tseng, Jui-Han Lu, Chun-Ming Chen, Ping-Ruey Chou, Yen-Hsin Kuo, Tung-Lin Tsai, Yen-Hao Chang, Sheng-Hua Wu, Chia-Hua Chang, Wen-Ming Cheng
  • Publication number: 20250219160
    Abstract: An aluminum battery includes a positive electrode, a negative electrode, a separator, and an electrolyte. The separator is disposed between the positive electrode and the negative electrode. The electrolyte is impregnated into the separator, the positive electrode, and the negative electrode. The electrolyte includes aluminum halide, ionic liquid, and an additive, and the additive includes an isocyanate compound.
    Type: Application
    Filed: July 9, 2024
    Publication date: July 3, 2025
    Applicant: APh ePower Co., Ltd.
    Inventors: Jui-Hsuan Wu, Shih Po Ta Tsai, Chun-Chieh Yang, Wei-An Chen
  • Patent number: 12349309
    Abstract: Provided is a centrifugal heat dissipation fan including a housing and an impeller. The impeller is disposed in the housing. The impeller has a hub and multiple blades disposed surrounding the hub. Every two adjacent blades have different blade structures relative to the housing such that the blade structures pass by a fixed position of the housing and generate blade tones of varying frequencies when the impeller rotates.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: July 1, 2025
    Assignee: Acer Incorporated
    Inventors: Yu-Ming Lin, Wen-Neng Liao, Cheng-Wen Hsieh, Tsung-Ting Chen, Sheng-Yan Chen, Chun-Chieh Wang
  • Publication number: 20250212417
    Abstract: A semiconductor structure includes a gate layer, a ferroelectric layer, a source structure, a drain structure, an oxide semiconductor and a high-k material layer. The gate layer is disposed in an interconnect structure. The ferroelectric layer is disposed over the gate layer. The source structure and the drain structure are disposed over the ferroelectric layer. The oxide semiconductor is disposed over the ferroelectric layer and between the source structure and the drain structure. The high-k material layer is disposed on and contacts a surface of the ferroelectric layer. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: December 25, 2023
    Publication date: June 26, 2025
    Inventors: YU-CHUAN SHIH, CHUN-CHIEH LU, KUO-CHANG CHIANG, CHIH-YU CHANG, HUAI-YING HUANG, YU-MING LIN
  • Publication number: 20250205232
    Abstract: The present invention features a compound of formula I: or a pharmaceutically acceptable salt thereof, where R1, R2, R3, W, X, Y, Z, n, o, p, and q are defined herein, for the treatment of CFTR mediated diseases, such as cystic fibrosis. The present invention also features pharmaceutical compositions, method of treating, and kits thereof.
    Type: Application
    Filed: July 17, 2024
    Publication date: June 26, 2025
    Applicant: Vertex Pharmaceuticals Incorporated
    Inventors: Mark Thomas Miller, Corey Anderson, Vijayalaksmi Arumugam, Brian Richard Bear, Hayley Marie Binch, Jeremy J. Clemens, Thomas Cleveland, Erica Conroy, Timothy Richard Coon, Bryan A. Frieman, Peter Diederik Jan Grootenhuis, Raymond Stanley Gross, Sara Sabina Hadida-Ruah, Haripada Khatuya, Pramod Virupax Joshi, Paul John Krenitsky, Chun-Chieh Lin, Gulin Erdogan Marelius, Vito Melillo, Jason McCartney, Georgia McGaughey Nicholls, Fabrice Jean Denis Pierre, Alina Silina, Andreas P. Termin, Johnny Uy, Jinglan Zhou
  • Publication number: 20250206156
    Abstract: A DC coupling power system receives an AC voltage from an AC power source and includes an AC/DC converter, a battery module, a DC coupled charger and a control unit. The AC/DC converter is configured to convert the AC voltage into a first DC voltage, and provide the first DC voltage and a supply power to a DC bus. The battery module is directly connected to the DC bus. The DC coupled charger receives the first DC voltage and provides a load power to charge a load. The control unit is configured to determine an energy of the battery module and compare the load power and a contracted demand capacity to set the AC/DC converter in one of a plurality of modes.
    Type: Application
    Filed: December 20, 2024
    Publication date: June 26, 2025
    Inventors: Chin-Ming CHEN, Chun-Chieh WU
  • Publication number: 20250201919
    Abstract: An aluminum battery includes a positive electrode, a negative electrode, a separator, and an electrolyte. The separator is disposed between the positive electrode and the negative electrode. The electrolyte is impregnated into the separator, the positive electrode, and the negative electrode. The electrolyte includes aluminum halide, ionic liquid, and an additive, and the additive includes a pyridine compound. The pyridine compound has an electron withdrawing functional group.
    Type: Application
    Filed: July 4, 2024
    Publication date: June 19, 2025
    Applicant: APh ePower Co., Ltd.
    Inventors: Jui-Hsuan Wu, Shih Po Ta Tsai, Chun-Chieh Yang, Wei-Chieh Hung
  • Publication number: 20250191912
    Abstract: A method includes: forming a bottom electrode over a substrate; depositing a first seed layer over the bottom electrode; performing a first surface treatment on the first seed layer to convert a crystal phase of the first seed layer; depositing a dielectric layer over the bottom electrode adjacent to the first seed layer; depositing an upper layer over the dielectric layer; and performing a thermal operation on the dielectric layer subsequent to the first surface treatment to thereby convert the dielectric layer into a ferroelectric layer.
    Type: Application
    Filed: February 19, 2025
    Publication date: June 12, 2025
    Inventors: CHUN-CHIEH LU, SAI-HOOI YEONG, YU-MING LIN
  • Publication number: 20250186678
    Abstract: A negative pressure medical device includes a suction component and a care component. The suction component includes a cylinder body having a chamber. One end of the cylinder body has a suction port connected to the chamber. The other end of the cylinder body opposite the suction port has an insertion port. A plunger rod is disposed in the chamber, such that the plunger rod is movable in a direction along the suction port and the insertion port. The plunger rod abuts an inner peripheral wall of the cylinder body by an airtight component. The care component is configured to cover skin around a wound area of a user to maintain a negative pressure environment between the care component and the wound area. The care component is connected to the suction port of the suction component, such that gas of the negative pressure environment flows unidirectionally to the suction component.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Inventors: Yur-Ren Kuo, Su-Shin Lee, Chun-Chieh Tseng, Chun-Ming Chen, Tung-Lin Tsai, Chia-Hua Chang, Ling-Zhen Kao
  • Patent number: 12321541
    Abstract: A touch pad device includes a base unit, a touch unit and a resilient unit. The base unit includes a bottom plate and a supporting member disposed on the bottom plate. The touch unit includes a touch pad, a circuit board connected to the touch pad, and a switch button disposed the circuit board. The switch button corresponds in position to the supporting member. The resilient unit is disposed between the bottom plate and the circuit board, and includes a resilient plate connected to the bottom plate, and a reinforcing frame connected between the resilient plate and the circuit board. The resilient plate has two resilient piece portions, and an abutment portion connected to the resilient piece portions and supported by the supporting member. The abutment portion is positioned between the switch button and the supporting member. The reinforcing frame is connected to the resilient piece portions.
    Type: Grant
    Filed: June 27, 2024
    Date of Patent: June 3, 2025
    Assignee: SUNREX TECHNOLOGY CORP.
    Inventors: Chun-Chieh Chen, Yi-Wen Tsai
  • Patent number: 12322698
    Abstract: A method for forming a semiconductor memory structure includes forming a plurality of conductive wire structures over a semiconductor substrate, and forming a plurality of spacer structures along the sidewalls of the conductive wire structures. Each of the spacer structures includes a first spacer. The method also includes forming a plurality of dielectric strips across the conductive wire structures, forming a plurality of conductive strips over the conductive wire structures and the dielectric strips, performing a patterning process on the conductive strips to form a plurality of conductive pads, and removing the first spacer of each of the spacer structures to form a gap in each of the spacer structures.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: June 3, 2025
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Hung-Jung Yan, Ling-Chun Tseng, Chun-Chieh Wang, Tzu-Ming Ou Yang
  • Patent number: 12324194
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a gate, a ferroelectric layer disposed on the gate; a first channel layer disposed on the ferroelectric layer, a second channel layer disposed on the ferroelectric layer, and source and drain regions disposed on the first channel layer. The first channel layer includes a first thickness and the second channel layer includes a second thickness. A ratio of the first thickness and the second thickness is less than ?.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: June 3, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Chang, Chun-Chieh Lu, Yu-Chien Chiu, Ya-Yun Cheng, Yu-Ming Lin, Sai-Hooi Yeong, Hung-Wei Li