Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261043
    Abstract: A method includes: forming a bottom electrode over a substrate; depositing a first seed layer over the bottom electrode, the first seed layer having an amorphous crystal phase; performing a first surface treatment on the first seed layer, wherein after the first surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom electrode adjacent to the first seed layer; depositing an upper layer over the dielectric layer; and performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.
    Type: Grant
    Filed: November 15, 2023
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Yu-Ming Lin
  • Publication number: 20250095724
    Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.
    Type: Application
    Filed: December 2, 2024
    Publication date: March 20, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Li-Ping Huang, Yu-Fang Chen, Chun-Yen Tseng, Tzu- Feng Chang, Chun-Chieh Chang
  • Patent number: 12255392
    Abstract: A wideband antenna system includes a first metal radiation portion, having a coupling distance with a second metal radiation portion; a first feeding contact and a second feeding contact, electrically connected to the first metal radiation portion and the second metal radiation portion respectively, and close to the coupling distance; a first ground contact, electrically connected to the second metal radiation portion; a second ground contact, electrically connected to the first metal radiation portion; an impedance tuner, electrically connected to the first feeding contact, the second feeding contact, the first ground contact, the second ground contact, and a radio frequency signal source, to switch the first metal radiation portion and the second metal radiation portion; an aperture contact, electrically connected to the first metal radiation portion; and an aperture tuner, electrically connected to the aperture contact.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: March 18, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chun-Chieh Su, Wei-Cheng Lo, Chien-Ming Hsu, Che-Yen Lin, Chuan-Chien Huang
  • Publication number: 20250087433
    Abstract: The present invention provides a key plugging structure, a key assembly and a keyboard. The key plugging structure includes a circuit board, a socket member and an elastic member. The circuit board includes a through hole penetrating through the circuit board. The socket member includes a slot and a first jack hole, the first jack hole is formed at the bottom of the slot; the socket member is embedded in the through hole; the first jack hole and the through hole are connected to each other; the elastic member has a second jack hole; the elastic member is assembled in the hole slot; the second socket hole and the first socket hole are connected with each other. Further, the key assembly includes a key. The redesign for the socket of the key plugging structure embedded in the circuit board reduce the height of the key assembly.
    Type: Application
    Filed: September 11, 2024
    Publication date: March 13, 2025
    Inventor: Chun-Chieh WU
  • Publication number: 20250073451
    Abstract: An in vitro training method for training genioglossus muscle strength includes adhering an electrode patch of an in vitro training device to a bottom of a chin of a user during a non-sleep period. The electrode patch receives an electrical stimulation signal from an electrical stimulation module of the in vitro training device to stimulate the genioglossus muscle of the user through transdermal electrical stimulation. The electrode patch includes a body surface adhering face and an assembling face opposite to the body surface adhering face. The body surface adhering face is adhered to the bottom of the chin of the user to align with the genioglossus muscle. The electrical stimulation module is disposed on the assembling face and in electrical connection with the electrode patch. The electrical stimulation module sends an electrical stimulation signal to stimulate the genioglossus muscle through transdermal electrical stimulation.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 6, 2025
    Inventors: Bol-Wei Huang, Yu-Sheng Lin, Tung-Lin Tsai, Chun-Chieh Tseng
  • Publication number: 20250077001
    Abstract: A touch pad device includes a base unit, a touch unit and a resilient unit. The base unit includes a bottom plate and a supporting member disposed on the bottom plate. The touch unit includes a touch pad, a circuit board connected to the touch pad, and a switch button disposed the circuit board. The switch button corresponds in position to the supporting member. The resilient unit is disposed between the bottom plate and the circuit board, and includes a resilient plate connected to the bottom plate, and a reinforcing frame connected between the resilient plate and the circuit board. The resilient plate has two resilient piece portions, and an abutment portion connected to the resilient piece portions and supported by the supporting member. The abutment portion is positioned between the switch button and the supporting member. The reinforcing frame is connected to the resilient piece portions.
    Type: Application
    Filed: June 27, 2024
    Publication date: March 6, 2025
    Inventors: Chun-Chieh CHEN, Yi-Wen TSAI
  • Patent number: 12243218
    Abstract: The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Hsuan Lee, Chien-Hsiang Huang, Kuang-Shing Chen, Kuan-Hsin Chen, Chun-Chieh Chin
  • Patent number: 12242677
    Abstract: A full-area touch device includes a linkage unit disposed between a base unit and a touch control unit to drive a trigger switch of the touch control unit to be triggered by the base unit. The linkage unit is symmetrical relative to the trigger switch and includes an outer frame, an inner frame, linkage members fixed between the outer and inner frames, and a left plate and a right plate fixed to the base unit in the inner frame. A left front linkage member and a left rear linkage member are fixed between the left plate and the inner frame. A right front linkage member and a right rear linkage member are fixed between the right plate and the inner frame. A portion of an outer frame space not occupied by the base unit, the inner frame, the left plate and the right plate is defined as a floating chamber.
    Type: Grant
    Filed: April 3, 2024
    Date of Patent: March 4, 2025
    Assignee: SUNREX TECHNOLOGY CORP.
    Inventors: Chun-Chieh Chen, Ling-Cheng Tseng
  • Publication number: 20250065110
    Abstract: An in vitro training method includes scanning a user's oral cavity to create a first oral cavity model. An articulator body is selected according to the first oral cavity model, and plural first customized electrode sheets are formed and assembled onto the articulator body to obtain an in vitro training device. The user bites the in vitro training device during a non-sleep period and uses the plural first customized electrode sheets to proceed with electrical stimulation on a top surface and two sides of a tongue of the user, thereby training a muscular endurance of infrahyoid muscles of the user for a training period. The user's oral cavity is scanned again to create a second oral cavity model. The first oral cavity model is compared with the second oral cavity model to timely renew the customized electrode sheets when the image over rate is lower than 80%.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 27, 2025
    Inventors: BOL-WEI HUANG, YU-SHENG LIN, TUNG-LIN TSAI, CHUN-CHIEH TSENG
  • Patent number: 12235197
    Abstract: An automatic processing device for liquid samples includes a sample region, a control module, an image identification device and a centrifuge. The sample region is configured to accommodate a plurality of centrifuge tubes. The control module includes a mechanical module. The mechanical module is configured to unscrew or tighten upper caps of the centrifuge tubes, and is configured to draw liquid from the centrifuge tubes or discharge liquid to the centrifuge tubes. The image identification device is coupled to the control module. The centrifuge is coupled to the control module. The centrifuge is configured to accommodate the centrifuge tubes and perform centrifugal treatment.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: February 25, 2025
    Assignees: CANCER FREE BIOTECH LTD., SONGYI SYSTEM CO., LTD.
    Inventors: Po-Han Chen, Shih-Pei Wu, Yi-Hsuan Chen, Chung-I Chen, Chun-Chieh Chiang, Chi-Ming Lee
  • Patent number: 12237395
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.
    Type: Grant
    Filed: February 20, 2022
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Wei Lin, Chun-Chieh Chiu, Chun-Ling Lin, Shu Min Huang, Hsin-Fu Huang
  • Patent number: 12234260
    Abstract: A Hepatitis E virus (HEV)-based virus like nanoparticle (HEVNP) made with a modified capsid protein containing at least a portion of open reading frame 2 (ORF2) protein conjugated with gold nanocluster is provided. Also provided are methods of targeted delivery of a nucleic acid using the HEVNP.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: February 25, 2025
    Assignee: The Regents of the University of California
    Inventors: R. Holland Cheng, Chun Chieh Chen, Mohammad Ali Baikoghli, Marie Stark
  • Patent number: 12239033
    Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Mo, Shih-Chi Kuo
  • Patent number: 12236115
    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
    Type: Grant
    Filed: January 15, 2024
    Date of Patent: February 25, 2025
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
  • Publication number: 20250062086
    Abstract: A keyboard including a key module is provided. The key module includes a keycap, a rigid modular circuit board and a linkage element. The linkage element is located between the keycap and the modular circuit board. The key module is detachably disposed on the keyboard, so that the key module, either in its entirety or as a part, could be disassembled from or assembled to the keyboard.
    Type: Application
    Filed: August 14, 2024
    Publication date: February 20, 2025
    Inventors: Cheng-Kun LIAO, Ming-Fu Yen, Wei-Jung Huang, Cheng-Hsiung Huang, Chun-Chieh Huang
  • Publication number: 20250063771
    Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Chao-Ching Cheng, Tzu-Ang Chao, Lain-Jong Li
  • Publication number: 20250063759
    Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
  • Publication number: 20250063866
    Abstract: A display apparatus includes a driving backplane, a plurality of light emitting components, a first bank layer and a plurality of scattering particles. The first bank layer is disposed on the driving backplane. The first bank layer has a plurality of first openings and a plurality of oblique surfaces defining the first openings. The light emitting components respectively overlap with the first openings of the first bank layer. The scattering particles are disposed on a plurality of light emitting surfaces of the light emitting components. A plurality of air gaps exist between the scattering particles and the oblique surfaces of the first bank layer.
    Type: Application
    Filed: December 27, 2023
    Publication date: February 20, 2025
    Inventors: Chun-Chieh Li, Sheng-Ming Huang, Han-Sheng Nian, Yu-Cheng Shih, Hsin-Hung Li
  • Publication number: 20250056809
    Abstract: A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Georgios Vellianitis, Marcus Johannes Henricus Van Dal, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: D1063925
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: February 25, 2025
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Po-Yang Chien, Hao-Jen Fang, Wei-Yi Chang, Chun-Chieh Chen, Chen-Cheng Wang, Chih-Wen Chiang, Sheng-Hung Lee