Patents by Inventor Chun-Chieh Wang

Chun-Chieh Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250063759
    Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
  • Publication number: 20250048620
    Abstract: A memory device and a manufacturing method are provided. The memory device includes active regions defined in a semiconductor substrate by an isolation structure, wherein the active regions are arranged as an array along first and second directions, and extend along a third direction; and word lines, extending through the active regions along the second direction in the semiconductor substrate. The active regions are arranged in pairs along the second direction. The active regions in the same pair are closely adjacent to each other by a first spacing. Adjacent pairs of the active regions are separated by a greater second spacing. A featured portion of each active region below an intersecting word line has a first side closely adjacent to the other active region in the same pair by the first spacing and a second side separated from another pair of the active regions by the second spacing, and has an inclined top surface ascending from the second side to the first side.
    Type: Application
    Filed: September 4, 2023
    Publication date: February 6, 2025
    Applicant: Winbond Electronics Corp.
    Inventors: Ying-Hung Chen, Chun-Chieh Wang, Tzu-Ming Ou Yang
  • Patent number: 12170202
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Grant
    Filed: January 2, 2023
    Date of Patent: December 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Patent number: 12166126
    Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
  • Patent number: 12151452
    Abstract: The present invention relates to a composite laminate plate, a housing and a mobile communication device. The composite laminate includes a top metal layer with a through hole and an array antenna, and an area ratio of the array antenna to the through hole meets a specific range, thereby enhancing wave transmissivity of a millimeter wave. Moreover, the composite laminate has a specific material structure, such that it has good mechanical properties and low density. The housing and the mobile communication device made by the composite laminate have advantages of metallic texture, high signal intensity and excellent effect for light weight tendency.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: November 26, 2024
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Yen-Lin Huang, Pei-Jung Tsai, Li-De Wang, Chun-Chieh Wang
  • Publication number: 20240379343
    Abstract: Embodiments of the disclosure relate to methods for reducing or eliminating the first wafer effect after chamber cleans for plasma etch processes. In some embodiments, the wafer support is maintained at an elevated temperature relative to the etch process. In some embodiments, the etch process is a NF3+NH3 plasma etch to remove native oxides from a silicon substrate.
    Type: Application
    Filed: May 10, 2024
    Publication date: November 14, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Yongqian Gao, Michael S. Jackson, David T. Or, Chun-Chieh Wang, Le Zhang
  • Patent number: 12140159
    Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.
    Type: Grant
    Filed: January 9, 2024
    Date of Patent: November 12, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20240371941
    Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. MORE, Huai-Tei Yang, Zheng-Yang Pan, Shin-Cieh Chang, Chun-Chieh Wang, Cheng-Han Lee
  • Publication number: 20240363350
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Publication number: 20240363442
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun Chieh Wang
  • Publication number: 20240363339
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
  • Patent number: 12117699
    Abstract: This invention discloses an etching solution and a manufacturing method of a display panel. The method includes following steps: providing a substrate; forming a conductive layer stack including a first sub-layer, a second sub-layer and a third sub-layer on the substrate, the first sub-layer includes molybdenum, the second sub-layer is disposed on the first sub-layer and includes a transparent conductive material including indium-containing oxide, the third sub-layer is disposed between the first sub-layer and the second sub-layer and includes silver or silver alloy; performing an etching process, the first sub-layer, the second sub-layer and the third sub-layer are etched by an etching solution to form a first patterned sub-layer, a second patterned sub-layer and a third patterned sub-layer. The etching solution includes 1 to 3 wt % of nitric acid, 30 to 50 wt % of acetic acid, 30 to 50 wt % of phosphoric acid and a remaining amount of water.
    Type: Grant
    Filed: April 17, 2024
    Date of Patent: October 15, 2024
    Assignee: HANNSTAR DISPLAY CORPORATION
    Inventors: Li-Fang Chiu, Ching-Chieh Lee, Chun-Chieh Wang
  • Patent number: 12107015
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun Chieh Wang
  • Patent number: 12087575
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
  • Patent number: 12080761
    Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang, Cheng-Han Lee
  • Patent number: 12068545
    Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.
    Type: Grant
    Filed: August 18, 2023
    Date of Patent: August 20, 2024
    Assignee: HTC Corporation
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Publication number: 20240266439
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall surface of the gate structure. The semiconductor structure includes a source/drain (S/D) epitaxial layer formed adjacent to the gate structure, and a dielectric spacer layer formed on the S/D epitaxial layer. The semiconductor structure includes a contact plug barrier formed over the S/D epitaxial layer, and a contact plug surrounding by the contact plug barrier, wherein the contact plug is separated from the gate spacer layer by the dielectric spacer layer and the contact plug barrier.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 8, 2024
    Inventors: Chun-Chieh WANG, Yu-Ting LIN, Yueh-Ching PAI, Shih-Chieh CHANG, Huai-Tei YANG
  • Patent number: 12046823
    Abstract: A communication device includes a nonconductive track, an antenna element, a first turning wheel, and a second turning wheel. The antenna element is disposed on the nonconductive track. The first turning wheel and the second turning wheel drive the nonconductive track according to a control signal, so as to adjust the position of the antenna element. The communication device provides an almost omnidirectional radiation pattern.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: July 23, 2024
    Assignee: HTC CORPORATION
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Publication number: 20240243114
    Abstract: An electronic package structure includes first and second package modules combined with each other. The first package module includes a substrate and a first electronic component disposed thereon, at least one second electronic component, and an insulation film. The first electronic component and the second electronic component are adjacent to each other. The insulation film includes a base material and a foam glue body, and the foam glue body is viscous and compressible. The second package module includes a heat dissipation plate and a liquid metal and an insulation protrusion portion disposed thereon. The liquid metal is pressed by the heat dissipation plate and the first electronic component. The insulation protrusion portion covers and abuts against the insulation film to press the foam glue body through the base material so as to deform the foam glue body and enable the foam glue body to cover the second electronic component.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Applicant: Acer Incorporated
    Inventors: Yu-Ming Lin, Mao-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen, Kuan-Lin Chen, Chun-Chieh Wang
  • Publication number: 20240232101
    Abstract: The invention relates to a logic control device of a serial peripheral interface, a master-slave system and a master-slave switchover method therefor. The logic control device is connected between N masters and M slaves, and define master-slave connection relationships between each of the masters and each of the slaves. Each of the master-slave connection relationship is that each of the masters and each of the slaves transmit information one-to-one at the same time, and includes connecting the logic control device between the masters and the slaves to form the master-slave system as well as the master-slave switchover method therefor.
    Type: Application
    Filed: October 20, 2022
    Publication date: July 11, 2024
    Inventors: CHUN CHIEH WANG, CHENG YU WANG, JIN KAI YANG