Patents by Inventor Chun-Chieh Wang

Chun-Chieh Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210288029
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
  • Patent number: 11121159
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20210275138
    Abstract: An ultrasound image system is provided. The ultrasound image system includes an ultrasound probe and a processing circuit. The ultrasound probe includes a substrate, a first transducer array and a second transducer array. The first transducer array is fixed disposed on the substrate and configured to receive a first ultrasound signal The second transducer array is fixed disposed on the substrate and configured to receive a second ultrasound signal. Each of the first transducer array and the second transducer array includes a plurality of ultrasound transducer elements arranged along a first direction. The ultrasound transducer elements of the first transducer array are interleaved with the ultrasound transducer elements of the second transducer array. The processing circuit is coupled to the first transducer array and the second transducer array and is configured to generate an ultrasound image signal according to the first ultrasound signal and the second ultrasound signal.
    Type: Application
    Filed: March 8, 2020
    Publication date: September 9, 2021
    Inventors: Fu-Sheng Jiang, Chun-Chieh Wang
  • Publication number: 20210257263
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Application
    Filed: April 16, 2021
    Publication date: August 19, 2021
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun Chieh Wang
  • Publication number: 20210202327
    Abstract: In a method of manufacturing a semiconductor device, semiconductor layers, which are vertically arranged with a space between adjacent semiconductor layers, are provided over a substrate, an interfacial layer is formed around each of the semiconductor layers, a dielectric layer is formed on the interfacial layer around each of the semiconductor layers, a first conductive layer is formed on the dielectric layer, the first conductive layer is removed so that the dielectric layer is exposed, a second conductive layer is formed on the exposed dielectric layer so that the space between adjacent semiconductor layers is not fully filled by the second conductive layer, a third conductive layer is formed on the second conductive layer so that the space between adjacent semiconductor layers is filled by the third conductive layer, and the semiconductor layers are semiconductor wires or sheets.
    Type: Application
    Filed: July 24, 2020
    Publication date: July 1, 2021
    Inventors: Chun-Chieh WANG, Yueh-Ching PAI
  • Publication number: 20210194363
    Abstract: A time signal generating circuit of a power converter and a control method thereof are provided. The time signal generating circuit includes a reference frequency generating circuit, an on-time circuit and a frequency tracking circuit. The reference frequency generating circuit provides a reference frequency signal. The on-time circuit provides an on-time signal according to a first reference signal and a second reference signal. The second reference signal is related to an output voltage of the power converter. The frequency tracking circuit is coupled to the reference frequency generating circuit and the on-time circuit, and compares frequencies of the reference frequency signal and the on-time signal within a default time to generate a tracking signal. The on-time circuit adjusts the second reference signal according to the tracking signal, so that the on-time circuit adjusts the frequency of the on-time signal.
    Type: Application
    Filed: October 20, 2020
    Publication date: June 24, 2021
    Applicant: uPI Semiconductor Corp.
    Inventors: Chih-Lien Chang, Chun-Chieh Wang
  • Publication number: 20210165473
    Abstract: A portable electronic device including a body, a door, a carrier and at least one electronic module is provided. The door is movably mounted on the body. The carrier includes a first side and a second side opposite to each other, the first side is pivoted to the body, and the second side is movably pivoted to the door. The electronic module is disposed on the carrier. At least one opening is formed between the door and the body when the door moves away from the body, and the door drives the carrier to rotate relative to the body, such that the electronic module is tilted with respect to the body along with the movement of the door, and the electronic module is exposed to an external environment via the opening for heat dissipation.
    Type: Application
    Filed: July 6, 2020
    Publication date: June 3, 2021
    Applicant: Acer Incorporated
    Inventors: Yi-Ta Huang, Chun-Chieh Wang, Wu-Chen Lee, Cheng-Nan Ling, Cheng-Wen Hsieh
  • Patent number: 11011433
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Publication number: 20210143278
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.
    Type: Application
    Filed: January 22, 2021
    Publication date: May 13, 2021
    Inventors: Chun-Chieh WANG, Yu-Ting LIN, Yueh-Ching PAI, Shih-Chieh CHANG, Huai-Tei YANG
  • Publication number: 20210111625
    Abstract: The disclosure provides a power conversion circuit with a multi-function pin and a multi-function setting method thereof. The multi-function pin is coupled to an external setting circuit. The power conversion circuit includes a first function circuit, a second function circuit, and a judging circuit. The first function circuit is coupled to the multi-function pin. The second function circuit is coupled to the multi-function pin. The judging circuit is coupled to the multi-function pin, the first function circuit, and the second function circuit. The judging circuit provides a setting current to the multi-function pin, so that the external setting circuit generates a voltage according to the setting current. The judging circuit judges the type of external setting circuit according to voltage so as to activate the first function circuit or the second function circuit accordingly.
    Type: Application
    Filed: August 12, 2020
    Publication date: April 15, 2021
    Applicant: uPI Semiconductor Corp.
    Inventors: Chih-Lien Chang, Chun-Chieh Wang
  • Publication number: 20210111027
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Patent number: 10971602
    Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Shun Liao, Huai-Tei Yang, Chun Chieh Wang, Yueh-Ching Pai, Chun-I Wu
  • Publication number: 20210096242
    Abstract: An underwater ultrasonic device includes a curvilinear ultrasonic transducer and a plurality of straight linear ultrasonic transducers. The straight linear ultrasonic transducers are disposed with respect to the curvilinear ultrasonic transducer. A first angle is included between the straight linear ultrasonic transducers. One of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to transmit a plurality of ultrasonic signals. Another one of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals.
    Type: Application
    Filed: September 11, 2020
    Publication date: April 1, 2021
    Inventors: Fu-Sheng Jiang, Chun-Chieh Wang, Yi-Hsiang Chan, Heng-Yi Shiu, Hsin-Chih Liu
  • Patent number: 10955517
    Abstract: An underwater ultrasonic device includes at least one first ultrasonic transducer and at least one second ultrasonic transducer. The first ultrasonic transducer is configured to transmit a plurality of ultrasonic signals and the second ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals. The first ultrasonic transducer and the second ultrasonic transducer are disposed with respect to each other. One of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear and another one of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear or straight linear.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: March 23, 2021
    Assignee: Qisda Corporation
    Inventors: Fu-Sheng Jiang, Chun-Chieh Wang
  • Publication number: 20210079925
    Abstract: A data processing method is proposed, including: sensing, via at least one sensing portion, target information of a target device; receiving and processing, via an electronic device, the target information of the sensing portion to form feature information; processing, via the electronic device, the feature information into a label matrix, and establishing, via an artificial intelligence training method, a target model based on the label matrix; and after the electronic device captures real-time information of the target device, predicting, via the target model, a life limit of the target device, wherein a content of the target information is corresponding to a content of the real-time information. Thus, a good target model is constituted and is advantageous in training artificial intelligence by processing the feature information into the label matrix.
    Type: Application
    Filed: February 18, 2020
    Publication date: March 18, 2021
    Inventors: Ming-Hsiang Hsu, Chun-Chieh Wang, Hung-Tsai Wu
  • Publication number: 20210067062
    Abstract: Provided is an electronic device and an electric energy conversion method. The electronic device includes at least one moving component, a transducer system, a charging and discharging system, and a power supply system. The transducer system has at least one piezoelectric membrane and a storage unit. The at least one piezoelectric membrane is disposed on the at least one moving component, and the storage unit is electrically coupled to the at least one piezoelectric membrane. The charging and discharging system is electrically coupled to the at least one moving component and the transducer system. The power supply system is electrically coupled to the at least one moving component, the transducer system, and the charging and discharging system to provide main energy. The at least one moving component starts to operate, the at least one moving component leads the at least one piezoelectric membrane to deform elastically to generate assisting charges.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 4, 2021
    Applicant: Coretronic Corporation
    Inventors: Jui-Ta Liu, Chun-Chieh Wang, Chih-Hsiang Li, Kuo-Liang Peng
  • Patent number: 10937910
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Patent number: 10928869
    Abstract: A heat dissipation module including a chamber, a first cooling member, and a barrier part is provided. The chamber has an accommodating space, at least one inlet, and at least one outlet. The at least one inlet is disposed in a first side wall of the chamber and communicates with the accommodating space. The at least one outlet is disposed in a second side wall of the chamber away from the at least one inlet and communicates with the accommodating space. The first cooling member is disposed in the accommodating space. The first cooling member has a guiding surface which extends obliquely upward. The barrier part is disposed outside the guiding surface of the first cooling member and has at least one through hole.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 23, 2021
    Assignee: Acer Incorporated
    Inventors: Chun-Chieh Wang, Wen-Neng Liao, Cheng-Wen Hsieh, Wei-Chin Chen, Jau-Han Ke
  • Publication number: 20210040332
    Abstract: A fouling-proof structure is applicable to synthetic leather or fabric and it includes an alcohol-resistant layer; and a water-based fouling-proof layer disposed on the alcohol-resistant layer, wherein the alcohol-resistant layer is formed by curing an alcohol-resistant combination, and the alcohol-resistant combination comprises polyurethane resin, wherein the water-based fouling-proof layer is formed by curing a water-based fouling-proof combination, and the water-based fouling-proof combination comprises polyurethane resin, water, polymerized siloxanes, water-based PTFE and silicone oil.
    Type: Application
    Filed: March 6, 2020
    Publication date: February 11, 2021
    Inventors: CHING-HSIANG CHANG, KUO-HSING YEH, CHUN-CHIEH WANG
  • Publication number: 20210040349
    Abstract: A method of producing a fouling-proof structure, comprising steps of a) coating an alcohol-resistant combination on a substrate and then drying the alcohol-resistant combination at 80-160° C. to form an alcohol-resistant layer; and b) coating a water-based fouling-proof combination on the alcohol-resistant layer and then drying the water-based fouling-proof combination above 140° C. to form a water-based fouling-proof layer, wherein the alcohol-resistant layer is formed by curing an alcohol-resistant combination, and the alcohol-resistant combination comprises polyurethane resin, wherein the water-based fouling-proof layer is formed by curing a water-based fouling-proof combination, and the water-based fouling-proof combination comprises polyurethane resin, water, polymerized siloxanes, water-based PTFE and silicone oil.
    Type: Application
    Filed: March 6, 2020
    Publication date: February 11, 2021
    Inventors: CHING-HSIANG CHANG, KUO-HSING YEH, CHUN-CHIEH WANG