Patents by Inventor Chun-Chieh Wang

Chun-Chieh Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11574928
    Abstract: A semiconductor memory structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes spacers formed over opposite sides of the gate structure. The structure also includes source drain epitaxial structures formed on opposite sides of the gate structure beside the spacers. The gate structure includes a III-V ferroelectric layer formed between an interfacial layer and a gate electrode layer.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: February 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chenchen Jacob Wang, Sai-Hooi Yeong, Bo-Feng Young, Chun-Chieh Lu, Yu-Ming Lin
  • Publication number: 20230034360
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate stack wrapping around first nanostructures, a second gate stack wrapping around second nanostructures, a gate isolation structure interposing between the first gate stack and the second gate stack, a first source/drain feature adjoining the first nanostructures, a second source/drain feature adjoining the second nanostructures, and a source/drain spacer structure interposing between the first source/drain feature and the second source/drain feature. The gate isolation structure covers a sidewall of the source/drain spacer structure.
    Type: Application
    Filed: February 15, 2022
    Publication date: February 2, 2023
    Inventors: Huan-Chieh Su, Zhi-Chang Lin, Li-Zhen Yu, Chun-Yuan Chen, Lo-Heng Chang, Cheng-Chi Chuang, Chih-Hao Wang, Lin-Yu Huang
  • Patent number: 11569730
    Abstract: A power supply device includes a pulse frequency modulation controller circuitry and a cycle controller circuitry. The pulse frequency modulation controller circuitry is configured to adjust a transiting speed of a first signal according to at least one control bit, and to compare the first signal with a first reference voltage to generate a second signal, and to generate a driving signal to a power converter circuit according to an output voltage, a second reference voltage, and the second signal, in which the power converter circuit is configured to generate the output voltage according to the driving signal. The cycle controller circuitry is configured to detect a frequency of the driving signal according to a clock signal having a predetermined frequency, in which the predetermined frequency is set based on a frequency range capable of being heard by humans.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: January 31, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Cheng Wang, Hung-Wan Liu, Shih-Chieh Chen, Chun-Fu Chang, Liang-Hui Li
  • Publication number: 20230024309
    Abstract: A method of generating point cloud predictor includes: obtaining an encoding unit, wherein the encoding unit is generated from a current three-dimensional (3D) image, obtaining a current 3D block in the current 3D image according to the encoding unit, obtaining a reference 3D block in a reference 3D image according to the current 3D block, wherein the reference 3D image is associated with the current 3D image, obtaining a reference two-dimensional (2D) unit in a reference 2D image according to the reference 3D block, wherein the reference 2D image is generated from the reference 3D image, and generating and outputting a predictor according to a variation degree between the encoding unit and the reference 2D unit.
    Type: Application
    Filed: December 24, 2021
    Publication date: January 26, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jie-Ru LIN, Ching-Chieh LIN, Sheng-Po WANG, Chun-Lung LIN
  • Publication number: 20230021460
    Abstract: A feature data encoding method, an encoder, a feature data decoding method, and a decoder are provided. The feature data encoding method includes following steps. A transform unit is divided into a plurality of sub-blocks and N sub-transform units. A reference origin and a LSC are determined in an i-th sub-transform unit of the sub-transform units, and an original coordinate of the last significant coefficient of the i-th sub-transform unit is modified to a specific coordinate. The i-th sub-transform unit is scanned from a specific sub-block of the i-th sub-transform unit, and significant feature coefficients in the i-th sub-transform unit are individually encoded as coded data.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 26, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Sheng-Po Wang, Ching-Chieh Lin, Chun-Lung Lin
  • Patent number: 11555981
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 17, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20230005189
    Abstract: A content patch encoding method and a content patch decoding method are provided. The content patch decoding method includes: receiving a bit stream, and obtaining multiple information corresponding to a point cloud patch and a mesh patch accordingly; obtaining a connectivity between multiple vertices of the mesh patch based on the bit stream; and reconstructing the point cloud patch and the mesh patch based on the information and the connectivity between the vertices.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 5, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Jie-Ru Lin, Ching-Chieh Lin, Chun-Lung Lin, Sheng-Po Wang, Jih-Sheng Tu
  • Patent number: 11545363
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Publication number: 20220416789
    Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.
    Type: Application
    Filed: March 15, 2022
    Publication date: December 29, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Chao-Min Lai, Han-Chieh Hsieh, Tang-Hung Chang, Hung-Wei Wang, Chun-Yi Kuo
  • Patent number: 11532744
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, a gate cut feature extending continuously from between the first gate structure and the second gate structure to between the first backside dielectric feature and the second backside dielectric feature, and a liner disposed between the gate cut feature and the first backside dielectric feature and between the gate cut feature and the second backside dielectric feature.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220400581
    Abstract: A portable electronic device including a first body, a second body, a heat source, a first heat pipe, a second heat pipe, and a heat conducting element is provided. The second body is pivotally connected to the first body. The heat source is disposed in the first body and thermally coupled to the heat source. The second heat pipe is disposed in the first body and thermally coupled to the first heat pipe. The heat conducting element is connected to and thermally coupled to the second body, and the heat conducting element slidably contacts the second heat pipe and is thermally coupled to the second heat pipe.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 15, 2022
    Applicant: Acer Incorporated
    Inventors: Chun-Chieh Wang, Wen-Neng Liao, Cheng-Wen Hsieh, Tsung-Ting Chen
  • Patent number: 11527655
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Publication number: 20220384403
    Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 1, 2022
    Inventors: Tung-Kai LIU, Tsau-Hua HSIEH, Wei-Cheng CHU, Chun-Hsien LIN, Chandra LIUS, Ting-Kai HUNG, Kuan-Feng LEE, Ming-Chang LIN, Tzu-Min YAN, Hui-Chieh WANG
  • Publication number: 20220384602
    Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface, a first sidewall of the source epitaxial structure, and a second sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh SU, Li-Zhen YU, Chun-Yuan CHEN, Cheng-Chi CHUANG, Shang-Wen CHANG, Yi-Hsun CHIU, Pei-Yu WANG, Ching-Wei TSAI, Chih-Hao WANG
  • Publication number: 20220384483
    Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chi On Chui, Han-Jong Chia, Chenchen Jacob Wang
  • Publication number: 20220384244
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 1, 2022
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
  • Publication number: 20220384590
    Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen, Li-Zhen Yu, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11515231
    Abstract: A coating method applied to perform coating with liquid metal thermal grease and a heat dissipation module are provided. The coating method includes: providing liquid metal thermal grease on a surface of an electronic element, and scraping the liquid metal thermal grease by a scraper, to coat the surface of the electronic element with the liquid metal thermal grease. A surface of the scraper is roughened. According to the coating method, the surface of the electronic element is evenly coated with the liquid metal thermal grease effectively.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: November 29, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chia-Chang Lee, Chun-Chieh Wong, Cheng-Yu Wang, Tai-Min Hsu, Yao-Jen Chang
  • Publication number: 20220376079
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
  • Patent number: 11509320
    Abstract: A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device having a first input terminal and a second input terminal for receiving a first received signal and a second received signal, and for generating an output signal at an output port. The first digital-slope quantizer generates a first set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer generates a second set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a second phase after the first phase according to a second quantization unit.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: November 22, 2022
    Assignee: TRON FUTURE TECH INC.
    Inventors: Yu-Jiu Wang, Chun-Chieh Peng, Ta-Shun Chu