Abstract: A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: A method includes depositing an inter-layer dielectric (ILD) over a source/drain region; forming a contact opening through the ILD, wherein the contact opening exposes the source/drain region; forming a metal-semiconductor alloy region on the source/drain region; depositing a first layer of a conductive material on the metal-semiconductor alloy region; depositing an isolation material along sidewalls of the contact opening and over the first layer of the conductive material; etching the isolation material to expose the first layer of the conductive material, wherein the isolation material extends along sidewalls of the contact opening after etching the isolation material; and depositing a second layer of the conductive material on the first layer of the conductive material.

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

Abstract: Some implementations described herein provide a gas curtain system. The gas curtain system includes various components to prevent a gas flowing within a chamber of an interface tool from flowing through an opening into a transport carrier adjacent to the interface tool. The gas curtain system may include a gas distribution component along an edge of the opening that generates a flow of another gas across the opening towards an opposite edge of the opening. In this way, the gas from the chamber is prevented from entering the transport carrier. By preventing the gas from the chamber from entering the transport carrier, a relative humidity within an environment of the transport carrier is maintained such that condensation of moisture on one or more semiconductor wafers within the transport carrier is mitigated.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.

Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.