Patents by Inventor Chun-Hsien YU

Chun-Hsien YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250053210
    Abstract: A laptop computer including a host, a movable door, a display, an input module, and a fan is provided. The host has a first surface and a second surface opposite to each other. The movable door is disposed on the second surface. The display is pivoted to the host to be folding on the first surface or unfolding from the first surface. The input module is disposed on the first surface. The fan is disposed in the host, and the movable door covers the fan. When the movable door is removed from the fan, an impeller of the fan is exposed from the host via the second surface.
    Type: Application
    Filed: January 19, 2024
    Publication date: February 13, 2025
    Applicant: Acer Incorporated
    Inventors: Chun-Hung Wen, Hui-Ping Sun, Chun-Hsien Chen, Jui-Yi Yu, Yen-Chou Chueh
  • Patent number: 12154866
    Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: November 26, 2024
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
  • Patent number: 12094922
    Abstract: An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: September 17, 2024
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Patent number: 11887299
    Abstract: An image processing system includes an ophthalmoscope device and a processor. The ophthalmoscope device is configured to obtain a color fundus image. The processor is configured to receive the color fundus image; generate a blood vessel segmentation image that corresponds to the color fundus image using a computer vision algorithm or a deep learning model; preprocess the color fundus image and the blood vessel segmentation image to obtain an initial input image; and input the initial input image into a convolutional neural network. The convolutional neural network outputs a value. In addition, the processor generates fundus image analysis information from the cup-to-disc ratio and the value.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: January 30, 2024
    Assignees: ACER INCORPORATED, NATIONAL TAIWAN UNIVERSITY HOSPITAL
    Inventors: Chun-Hsien Yu, Jehn-Yu Huang, Cheng-Tien Hsieh, Yun-Ting Lin
  • Patent number: 11791281
    Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 17, 2023
    Assignees: ADVANCED SEMICONDUCTOR ENGINEERING, INC., PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: You-Lung Yen, Pao-Hung Chou, Chun-Hsien Yu
  • Patent number: 11749619
    Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 5, 2023
    Assignees: ADVANCED SEMICONDUCTOR ENGINEERING, INC., PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: You-Lung Yen, Pao-Hung Chou, Chun-Hsien Yu
  • Patent number: 11749612
    Abstract: A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: September 5, 2023
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Hsien-Ming Tsai
  • Patent number: 11646331
    Abstract: This disclosure provides a package substrate including: a first dielectric layer formed of a first molding compound; a first conductive wire and a first conductive channel disposed in the first dielectric layer; a second dielectric layer formed of a second molding compound; a second conductive wire and a second conductive channel disposed in the second dielectric layer; a third dielectric layer formed of a third molding compound; a third conductive wire and a third conductive channel disposed in the third dielectric layer; a fourth dielectric layer formed of a fourth molding compound; a fourth conductive wire, a fourth conductive channel and a circuit device disposed in the fourth dielectric layer; wherein, a first empty region, a second empty region, a third empty region and a fourth empty region are formed in the first, second, third and fourth dielectric layers, respectively, and the empty regions are vertically overlapped.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 9, 2023
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Hsien-Ming Tsai
  • Publication number: 20220406734
    Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.
    Type: Application
    Filed: August 19, 2022
    Publication date: December 22, 2022
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
  • Patent number: 11508673
    Abstract: A semiconductor packaging substrate is provided and includes: an insulating layer, a thinned circuit structure formed of circuit layers and conductive posts stacked on one another embedding in the insulating layer, and a supporting structure formed on the insulating layer and having at least one through hole exposing the conductive posts. As such, before a subsequent packaging operation, the packaging substrate can be electrically tested and screened so as to prevent a defective packaging substrate from being misused in the subsequent packaging operation and hence avoid the loss of normal electronic elements. A method for fabricating a semiconductor packaging substrate and a packaging process using the semiconductor packaging substrate are also provided.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 22, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu
  • Patent number: 11483939
    Abstract: An electronic device with a display interface is provided. The electronic device includes a device body and a display module. The device body includes a groove. The display module is disposed on the device body, wherein the display module includes a shaft, the shaft is rotatably connected to the groove and is adapted to be slid in the groove, and the extension direction of the groove differs from the axis of the shaft.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: October 25, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: You-Lin Li, Chun-Hsien Yu
  • Patent number: 11476204
    Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 18, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
  • Publication number: 20220328613
    Abstract: An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.
    Type: Application
    Filed: March 4, 2022
    Publication date: October 13, 2022
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Patent number: 11455498
    Abstract: A model training method and an electronic device are provided. The method includes the following steps: establishing a brain age prediction model according to a training set; adjusting a parameter in the brain age prediction model according to a validation set; inputting a test set into the brain age prediction model with the adjusted parameter to obtain a plurality of first predicted brain ages; determining whether the first predicted brain ages satisfy a first specific condition; and completing training of the brain age prediction model when the first predicted brain ages satisfy the first specific condition.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: September 27, 2022
    Assignees: Acer Incorporated, National Yang-Ming University
    Inventors: Cheng-Tien Hsieh, Chun-Hsien Yu, Shih-Ho Huang, Meng-Che Cheng, Kun-Hsien Chou, Ching-Po Lin, Liang-Kung Chen
  • Patent number: 11450597
    Abstract: A semiconductor package substrate, a method for fabricating the same, and an electronic package having the same are provided. The method includes: providing a circuit structure having a first solder pad and a second solder pad; forming on the circuit structure a metal sheet having a first hole, from which the first solder pad is exposed, and a second hole, from which the second solder pad is exposed; and forming an insulation layer on the metal sheet and a hole wall of the second hole. A first conductive element that is to be grounded is disposed in the first hole and is in contact with the metal sheet and the first solder pad. Therefore, heat generated in a signal transmission process is dissipated by the metal sheet and the first conductive element.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: September 20, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Patent number: 11404348
    Abstract: A semiconductor package carrier board, a method for fabricating the same, and an electronic package having the same are provided. The method includes forming on a circuit structure a graphene layer that acts as an insulation heat dissipating layer. Since the heat conductivity of the graphene layer is far greater than the heat conductivity of ink (about 0.4 W/m·k), which is used as solder resist, the heat of the semiconductor package carrier board can be conducted quickly, and thus can avoid the problem that the heat will be accumulated on the semiconductor package carrier board.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: August 2, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Wen-Chang Chen
  • Patent number: 11379722
    Abstract: The disclosure provides a method for training generative adversarial network (GAN), a method for generating images by using GAN, and a computer readable storage medium. The method may train the first generator of the GAN with available training samples belonging to the first type category and share the knowledge learnt by the first generator to the second generator. Accordingly, the second generator may learn to generate (fake) images belonging to the second type category even if there are no available training data during training the second generator.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 5, 2022
    Assignee: HTC Corporation
    Inventors: Edward Chang, Che-Han Chang, Chun-Hsien Yu, Szu-Ying Chen
  • Publication number: 20220173048
    Abstract: A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 2, 2022
    Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Hsien-Ming Tsai
  • Publication number: 20220164947
    Abstract: An image processing system includes an ophthalmoscope device and a processor. The ophthalmoscope device is configured to obtain a color fundus image. The processor is configured to receive the color fundus image; generate a blood vessel segmentation image that corresponds to the color fundus image using a computer vision algorithm or a deep learning model; preprocess the color fundus image and the blood vessel segmentation image to obtain an initial input image; and input the initial input image into a convolutional neural network. The convolutional neural network outputs a value. In addition, the processor generates fundus image analysis information from the cup-to-disc ratio and the value.
    Type: Application
    Filed: March 4, 2021
    Publication date: May 26, 2022
    Inventors: Chun-Hsien YU, Jehn-Yu HUANG, Cheng-Tien HSIEH, Yun-Ting LIN
  • Patent number: 11335630
    Abstract: A semiconductor packaging substrate and a method for fabricating the same are provided. The method includes forming a solder resist structure having a hole on a circuit structure, with a portion of the circuit structure exposed from the hole, and forming a cup-shaped solder stand on the exposed circuit layer and a hole wall of the hole. During a packaging process, the design of the solder stand increases a contact area of a solder tin ball with a metal material. Therefore, a bonding force between the solder tin ball and the solder stand is increased, and the solder tin ball can be protected from being broken or fell off. An electronic package having the semiconductor packaging substrate and a method for fabricating the electronic package are also provided.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 17, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu