Patents by Inventor Chun-Hsien YU

Chun-Hsien YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200065623
    Abstract: The disclosure provides a method for verifying training data, a training system, and a computer program produce. The method includes: receiving a labelled result with a plurality of bounding regions, wherein the labelled result corresponds to an image, the bounding regions are labelled by a plurality of annotators, the annotators comprises a first annotator and a second annotator, and the bounding region comprises a first bounding region labelled by the first annotator and a second bounding region labelled by the second annotator; and determining the first bounding region and the second bounding region respectively corresponds to different two target objects or corresponds to one target object according to a similarity between the first bounding region and the second bounding region.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 27, 2020
    Applicant: HTC Corporation
    Inventors: Hao-Cheng Kao, Chih-Yang Chen, Chun-Hsien Yu, Shan-Yi Yu, Edzer Lienson Wu, Che-Han Chang
  • Publication number: 20190348375
    Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 14, 2019
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
  • Publication number: 20190279925
    Abstract: A semiconductor package structure includes a chip and a substrate having a recess. The substrate includes a base dielectric layer as the bottom of the recess, and numbers of supporting dielectric layers as the side surfaces of the recess. The substrate further includes a base connecting layer in the base dielectric layer, and numbers of supporting connecting layers in the supporting dielectric layers. Portions of the base connecting layer exposed on the bottom of the recess are first connection pads, and portions of the base connecting layer exposed on the bottom of the base dielectric layer are bottom connection pads. The active surface of the chip is turned toward the base dielectric layer, and the chip is located on the bottom of the recess. The active surface of the chip is electrically connected to the first connection pads.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 12, 2019
    Inventors: Shih-Ping Hsu, Chun-Hsien Yu, Hsien-Ming Tsai
  • Patent number: 10366906
    Abstract: The present disclosure provides an electronic package, including a package substrate and an electronic component formed on the package substrate. The substrate includes an insulating portion, a wiring portion embedded in the insulating portion, and a metal board disposed on the insulating portion and in contact with the wiring portion. The metal board is provided with a plurality of electrical contacts and a heat dissipating portion. The metal board can maintain a predefined heat dissipation area via the heat dissipating portion, and be connected to a circuit board via the electrical contacts.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 30, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Hsien-Ming Tsai
  • Patent number: 10347575
    Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate comprises: a first dielectric material layer have an opening; a first conductive unit including a first part in the opening of the first dielectric material layer and a second part on the first dielectric material layer; and a second dielectric material layer covering the first conductive unit and the first dielectric material layer; wherein a height of the first conductive unit is larger than a thickness of the first dielectric material layer; wherein a cross-section of the second part is larger than that of the first part in the first conductive unit.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: July 9, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Pao-Hung Chou, Chi-Feng Peng
  • Patent number: 10278282
    Abstract: A substrate structure and a manufacturing method thereof are provided. The substrate structure comprises a metal carrier, a dielectric material layer, a first conductive wiring layer, a second conductive wiring layer and a conductive pillar layer. The first conductive wiring layer is disposed on a surface of the metal carrier. The dielectric material layer is disposed on a surface of the first conductive wiring layer. The conductive pillar layer is disposed inside the dielectric material layer, and located between the first conductive wiring layer and the second conductive wiring layer. The conductive pillar layer has at least one conductive pillar. The conductive pillar is electrically connected to the first conductive wiring layer and the second conductive wiring layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 30, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Hsien-Ming Tsai
  • Publication number: 20190108442
    Abstract: A machine learning system includes a memory and a processor. The processor is configured to access and execute at least one instruction from the memory to perform inputting raw data to a first partition of a neural network, in which the first partition at least comprises an activation function of the neural network. The activation function is applied to convert the raw data into irreversible metadata. The metadata is transmitted to a second partition of the neural network as inputs to generate a learning result corresponding to the raw data.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 11, 2019
    Inventors: Edward Chang, Chun-Nan Chou, Chun-Hsien Yu
  • Publication number: 20190074196
    Abstract: The present disclosure provides an electronic package, including a package substrate and an electronic component formed on the package substrate. The substrate includes an insulating portion, a wiring portion embedded in the insulating portion, and a metal board disposed on the insulating portion and in contact with the wiring portion. The metal board is provided with a plurality of electrical contacts and a heat dissipating portion. The metal board can maintain a predefined heat dissipation area via the heat dissipating portion, and be connected to a circuit board via the electrical contacts.
    Type: Application
    Filed: November 28, 2017
    Publication date: March 7, 2019
    Inventors: Chun-Hsien Yu, Hsien-Ming Tsai
  • Patent number: 9852977
    Abstract: This disclosure provides a package substrate which includes a rigid dielectric material layer, a first wiring layer having at least one first metal wire formed on the rigid dielectric material layer, and a first flexible dielectric material layer formed on the first wiring layer.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 26, 2017
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Pao-Hung Chou
  • Patent number: 9824964
    Abstract: This disclosure provides a package substrate, a package structure including the same and their fabrication methods. The package substrate comprises: a first wiring layer having a first metal wire and a first dielectric material layer surrounding the first metal wire; a conductive pillar layer formed on the first wiring layer and including a first metal pillar connected to the first metal wire and a molding compound layer surrounding the first metal pillar; a flexible material layer formed on the conductive pillar layer and including a first opening formed on the first metal pillar and exposing the first metal pillar; and a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the first metal pillar through the first opening, a second metal pillar formed on the second metal wire, and a protective layer surrounding the second metal wire and the second metal pillar.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 21, 2017
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Shih-Ping Hsu
  • Publication number: 20170287815
    Abstract: This disclosure provides a package substrate, a package structure including the same and their fabrication methods. The package substrate comprises: a first wiring layer having a first metal wire and a first dielectric material layer surrounding the first metal wire; a conductive pillar layer formed on the first wiring layer and including a first metal pillar connected to the first metal wire and a molding compound layer surrounding the first metal pillar; a flexible material layer formed on the conductive pillar layer and including a first opening formed on the first metal pillar and exposing the first metal pillar; and a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the first metal pillar through the first opening, a second metal pillar formed on the second metal wire, and a protective layer surrounding the second metal wire and the second metal pillar.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: CHUN-HSIEN YU, SHIH-PING HSU
  • Patent number: 9754982
    Abstract: A substrate structure is provided, including a first insulating layer, a first circuit layer embedded in and bonded to the first insulating layer; a plurality of first conductive posts formed in the first insulating layer and electrically connected to the first circuit layer, a second circuit layer formed on the first insulating layer and electrically connected to the first circuit layer through the first conductive posts, a plurality of second conductive posts and a plurality of conductive bumps formed on the second circuit layer, and a second insulating layer formed on the first insulating layer and encapsulating the second circuit layer, the second conductive posts and the conductive bumps. The second insulating layer has a cavity exposing the conductive bumps. When the substrate structure is applied to a camera lens, a sensor element can be disposed in the cavity to reduce the thickness of the overall packaging module.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: September 5, 2017
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Chu-Chin Hu, Shih-Ping Hsu
  • Publication number: 20170208683
    Abstract: A substrate structure and a manufacturing method thereof are provided. The substrate structure comprises a metal carrier, a dielectric material layer, a first conductive wiring layer, a second conductive wiring layer and a conductive pillar layer. The first conductive wiring layer is disposed on a surface of the metal carrier. The dielectric material layer is disposed on a surface of the first conductive wiring layer. The conductive pillar layer is disposed inside the dielectric material layer, and located between the first conductive wiring layer and the second conductive wiring layer. The conductive pillar layer has at least one conductive pillar. The conductive pillar is electrically connected to the first conductive wiring layer and the second conductive wiring layer.
    Type: Application
    Filed: December 28, 2016
    Publication date: July 20, 2017
    Inventors: Chun-Hsien Yu, Hsien-Ming Tsai
  • Patent number: 9711445
    Abstract: This disclosure provides a package substrate, a package structure including the same and their fabrication methods. The package substrate comprises: a first wiring layer having a first metal wire and a first dielectric material layer surrounding the first metal wire; a conductive pillar layer formed on the first wiring layer and including a first metal pillar connected to the first metal wire and a molding compound layer surrounding the first metal pillar; a flexible material layer formed on the conductive pillar layer and including a first opening formed on the first metal pillar and exposing the first metal pillar; and a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the first metal pillar through the first opening, a second metal pillar formed on the second metal wire, and a protective layer surrounding the second metal wire and the second metal pillar.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: July 18, 2017
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Shih-Ping Hsu
  • Publication number: 20170198406
    Abstract: This disclosure provides a package substrate fabrication method including: providing a carrier; forming a first dielectric layer on the carrier while enabling the first dielectric layer to be patterned including an opening; forming a first conducting unit on the carrier while enabling the first conducting unit to fill up the opening, a height of the first conducting unit at the opening larger than a thickness of the first dielectric layer, and a width of the first conducting unit larger than a width of the opening; forming a second dielectric layer on the first conducting unit; forming a second conducting unit on the second dielectric layer; forming a third dielectric layer on the second conducting unit; removing the carrier and the first dielectric layer while enabling the part of the first conducting unit in the opening to be removed; and forming a fourth dielectric layer to cover the first conducting unit.
    Type: Application
    Filed: December 8, 2016
    Publication date: July 13, 2017
    Inventors: CHUN-HSIEN YU, SHIH-PING HSU, PAO-HUNG CHOU
  • Publication number: 20170148724
    Abstract: This disclosure provides a package substrate which includes a rigid dielectric material layer, a first wiring layer having at least one first metal wire formed on the rigid dielectric material layer, and a first flexible dielectric material layer formed on the first wiring layer.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 25, 2017
    Inventors: CHUN-HSIEN YU, PAO-HUNG CHOU
  • Publication number: 20170047278
    Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate comprises: a first dielectric material layer have an opening; a first conductive unit including a first part in the opening of the first dielectric material layer and a second part on the first dielectric material layer; and a second dielectric material layer covering the first conductive unit and the first dielectric material layer; wherein a height of the first conductive unit is larger than a thickness of the first dielectric material layer; wherein a cross-section of the second part is larger than that of the first part in the first conductive unit.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 16, 2017
    Inventors: CHUN-HSIEN YU, Shih-Ping Hsu, Pao-Hung Chou, Chi-Feng Peng
  • Publication number: 20160268326
    Abstract: A substrate structure is provided, including a first insulating layer, a first circuit layer embedded in and bonded to the first insulating layer; a plurality of first conductive posts formed in the first insulating layer and electrically connected to the first circuit layer, a second circuit layer formed on the first insulating layer and electrically connected to the first circuit layer through the first conductive posts, a plurality of second conductive posts and a plurality of conductive bumps formed on the second circuit layer, and a second insulating layer formed on the first insulating layer and encapsulating the second circuit layer, the second conductive posts and the conductive bumps. The second insulating layer has a cavity exposing the conductive bumps. When the substrate structure is applied to a camera lens, a sensor element can be disposed in the cavity to reduce the thickness of the overall packaging module.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 15, 2016
    Inventors: Chun-Hsien Yu, Chu-Chin Hu, Shih-Ping Hsu
  • Publication number: 20160260655
    Abstract: This disclosure provides a package substrate, a package structure including the same and their fabrication methods. The package substrate comprises: a first wiring layer having a first metal wire and a first dielectric material layer surrounding the first metal wire; a conductive pillar layer formed on the first wiring layer and including a first metal pillar connected to the first metal wire and a molding compound layer surrounding the first metal pillar; a flexible material layer formed on the conductive pillar layer and including a first opening formed on the first metal pillar and exposing the first metal pillar; and a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the first metal pillar through the first opening, a second metal pillar formed on the second metal wire, and a protective layer surrounding the second metal wire and the second metal pillar.
    Type: Application
    Filed: February 26, 2016
    Publication date: September 8, 2016
    Inventors: CHUN-HSIEN YU, SHIH-PING HSU
  • Patent number: 8837133
    Abstract: A display module includes a front frame, a rear housing, and a trimming board. The front frame includes a first positioning hole and a clamping hole. The rear housing includes a second positioning hole. The front frame is engaged with the rear housing. The second positioning hole communicates with the first positioning hole. The trimming board includes a bolt structure and a clamping structure. The bolt structure is adapted to pass through the first positioning hole and the second positioning hole for preventing the front frame from separated from the rear housing. The clamping hole is used for the clamping structure to pass through and prevent the clamping structure from separating from the clamping hole.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: September 16, 2014
    Assignee: Inventec Corporation
    Inventors: Dong-Sen Chen, Ming-Jheng Huang, Chun-Hsien Yu, Chun-Chi Lin