Abstract: A foldable electronic device, including a first body, a second body, an air valve movably disposed in the first body, at least one triggering member, and a hinge connecting the first body and the second body, is provided. The first body has multiple openings respectively located at two opposite surfaces. The triggering member is movably disposed in the first body and has a part exposed outside the first body. The air valve and the triggering member are mutually on moving paths of each other. The first body and the second body are rotated to be folded or unfolded relative to each other by the hinge. A part of the triggering member is suitable for bearing a force such that the triggering member drives the air valve, so that the air valve opens or closes the openings.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first semiconductor die, a second semiconductor die and a memory package. The first semiconductor die and the second semiconductor die are stacked on each other. The first semiconductor die includes a first interface and a third interface. The first interface overlaps and is electrically connected to the second interface arranged on the second semiconductor die. The third interface is arranged on a first edge of the first semiconductor die. The memory package is disposed beside the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die by the third interface.

Abstract: A foldable electronic device, including a first body having a first shaft member, at least one second body having a second shaft member, and a latching member, is provided. The first shaft member and the second shaft member are coaxially pivoted together. The first shaft member has a recess. The second shaft member has a locking hole. The latching member is movably disposed in the recess and the locking hole, so that when the latching member leaves the locking hole, the first body and the second body are relatively pivoted through the first shaft member and the second shaft member, or when the latching member moves into the locking hole, the latching member interferes with the first shaft member and the second shaft member to block the first body and the second body from relatively pivoting.

Abstract: An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.

Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.

Abstract: A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.

Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Abstract: A method of forming a semiconductor device includes forming first and second fin structures on a substrate, forming first and second gate stacks crossing the first and second fin structures, respectively, wherein the first fin structure has a first channel region under the first gate stack and a first source/drain region adjacent to the first channel region, and the second fin structure has a second channel region under the second gate stack and a second source/drain region adjacent to the second channel region, performing an ion implantation process to introduce impurities into the second source/drain region to form an implanted region in the second source/drain region, performing an etching process to form first and second recesses in the first and second source/drain regions, respectively, wherein the second recess penetrates through the implanted region, and forming epitaxy structures in the first and second recesses, respectively.

Abstract: A character recognition method includes the stages as detailed in the following paragraph. An image is received, wherein the image is one in a plurality of consecutive images. A target object in the image is detected. Object information of the target object is defined according to the area ratio of the target object occupied in the image. Whether the target object in the image is the same as the target object in the previous image is determined according to the object information. Character recognition on the target object is performed to obtain a recognition result. The weighting score of the recognition result is calculated according to the object information and the recognition result. The weighting score of the recognition result of the target object in the consecutive images is accumulated until the weighting score is higher than a preset value, and the recognition result is output.

Abstract: A reflector for a monocrystal furnace, the monocrystal furnace, and a method for processing the reflector. The inner contour line of the reflector comprises: a first straight line segment extending in a vertical direction, a second straight line segment having one end connected to the first straight line segment and the other end extending obliquely upward, and a line segment group; the included angle ? between the second straight line segment and the vertical direction is greater than or equal to 45°; the line segment group comprises a plurality of straight line segments which are sequentially connected and have different inclination angles, so as to transfer heat, transferred from an ingot to the line segment group, towards a water cooling jacket.

Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes: a first circuit, including a first semiconductor substrate, a first group of circuit components formed on the first semiconductor substrate, and a first group of metal layers, wherein, the first group of circuit components are distributed to at least one circuit block, and traces for each circuit block are formed in at least some of the first group of metal layers; a second circuit, including a second semiconductor substrate, a second group of circuit components formed on the second semiconductor substrate, and a second group of metal layers, wherein, the second group of circuit components are distributed to at least one circuit block, and traces for each circuit block are formed in at least some of the second group of metal layers, and the first circuit and the second circuit being face-to-face stacked and bonded.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first trench and a second trench in a first semiconductor material. The first trench is deeper than the second trench. The method also includes forming a second semiconductor material in the first trench and the second trench, patterning a first portion of the second semiconductor material in the first trench and a first portion of the first semiconductor material below the first portion of the second semiconductor material into a first fin structure, and patterning a second portion of the second semiconductor material in the second trench and a second portion of the first semiconductor material below the second portion of the second semiconductor material into a second fin structure, and forming an isolation structure surrounding the first fin structure and the second fin structure.

Abstract: A voltage regulating circuit includes a low-dropout regulator, configured to provide a driving voltage to drive a loading circuit and receive a first detection voltage from a first feedback terminal; and a reference voltage generating circuit, coupled to the low-dropout regulator, configured to receive a second detection voltage from a second feedback terminal. A voltage difference between the first feedback terminal and the second feedback terminal is clamped according to the first detection voltage and the second detection voltage.

Abstract: The present invention discloses a patient interface having an adaptive system, a respiratory mask and a cushion module adapted with the adaptive system. The adaptive system includes a forehead pressure diffusing portion, a cheek buffering portion and a connecting portion. The forehead pressure diffusing portion is disposed in a frame module. The cheek buffering portion is disposed in a cushion module. The connecting portion is positioned between the forehead pressure diffusing portion and the cheek buffering portion. The connecting portion is configured to transmit pressure between the forehead pressure diffusing portion and the cheek buffering portion. Thus, when a user wears a mask or other devices with the adaptive system, a force received by the face of the user could be automatically and appropriately distributed, further improving comfort of the wearer.

Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region of a first conductivity type. The semiconductor device structure also includes a first fin structure and an adjacent second fin structure formed in and protruding from the first well region. The semiconductor device structure also includes a first isolation structure formed in the first well region between the first fin structure and the second fin structure. A first sidewall surface of the first fin structure faces to a second sidewall surface of the second fin structure. The first sidewall surface and the second sidewall surface each extend along at least two directions from a bottom of the first isolation structure to a top of the first isolation structure.

Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.

Abstract: A graphite crucible for a mono-crystal furnace and a manufacturing method therefor, a crucible assembly, and a mono-crystal furnace. A groove is formed at a cutting portion. A thermal field simulation is performed on a semi-finished crucible product, a quartz crucible matching with the semi-finished crucible product and a melt to obtain an isotherm of a high temperature region of the melt. The shape of the groove is consistent with the shape of a part of the isotherm in a longitudinal section of a main body. The semi-finished crucible product is constructed such that the groove is produced on an inner wall of the semi-finished crucible product to form the main body.