Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, the patterned mask layer having a plurality of first features with a first pitch. The method includes patterning the material layer by using the patterned mask layer as a mask to form the first features in the material layer. The method includes trimming the patterned mask layer, after patterning the material layer, to form a trimmed patterned mask layer. The method further includes introducing a plurality of dopants into the material layer exposed by the trimmed patterned mask layer to form doped regions having a second pitch, wherein the second pitch is different from the first pitch. The method further includes removing the trimmed patterned mask layer to expose un-doped regions in the material layer; and removing the un-doped regions to form a plurality of second features corresponding to the respective doped regions.

Abstract: Systems and methods are provided for forming features through photolithography. A polymer layer is formed over a substrate. The polymer layer is patterned to form a first feature and a second feature, the first feature and the second feature being separated at a first distance. A rinse material is applied to the polymer layer including the first feature and the second feature. The rinse material is removed from the polymer layer including the first feature and the second feature to cause the first feature and the second feature to come into contact with each other. A third feature is formed based on the first feature and the second feature being in contact with each other.

Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, the patterned mask layer having a plurality of first features with a first pitch. The method includes patterning the material layer by using the patterned mask layer as a mask to form the first features in the material layer. The method includes trimming the patterned mask layer, after patterning the material layer, to form a trimmed patterned mask layer. The method further includes introducing a plurality of dopants into the material layer exposed by the trimmed patterned mask layer to form doped regions having a second pitch, wherein the second pitch is different from the first pitch. The method further includes removing the trimmed patterned mask layer to expose un-doped regions in the material layer; and removing the un-doped regions to form a plurality of second features corresponding to the respective doped regions.

Abstract: A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.

Abstract: An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresistlayer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresistlayer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant.

Abstract: A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.

Abstract: A structure of a semiconductor device including a substrate and a patterned layer is provided. The patterned layer being patterned to have an open area and a dense area is disposed on the substrate. The patterned layer includes, in the dense area, a first pattern adjacent to the open area and a second pattern. The first pattern has a first bottom. The second pattern has a second bottom width. The bottom of the first pattern includes a recess facing the open area, so that the first bottom width is close to the second bottom width.

Abstract: The present invention is applied in fields like biological medicine and tissue engineering. A fluid control system in a cell isolation and culture system is used to automatically process sample preparation, circulating tumor cell (CTC) isolation, plate changing and cell culturing. By using the present invention, time and labor are saved; moreover, the present invention has a small size and is easily carried.

Abstract: A water supply control method for a water tower connected to a server through a high water level sensor and a low water level sensor installed on the water tower. A solar panel is controlled to supply power to a motor of the water tower during off-peak hours and a current water level in the water tower has reached a lowest water level but has not reached a highest water level. An alternating current power supply is controlled to supply power to the motor during off-peak hours and the current water level in the water tower has not reached the lowest water level, or during peak hours and the current water level in the water tower has not reached the highest water level.

Abstract: A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O2 plasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The O2 plasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.

Abstract: A method for fabricating a patter is provided as followed. First, a material layer is provided, whereon a patterned hard mask layer is formed. A spacer is deposited on the sidewalls of the patterned hard mask layer. Then, the patterned hard mask layer is removed, and an opening is formed between the adjacent spacers. Afterwards, a portion of the material layer is removed to form a patterned material layer by using the spacer as mask.

Abstract: The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.

Abstract: The present invention is apllied in fields like biological medicine and tissue engineering. A fluid control system in a cell isolation and culture system is used to automatically process sample preparation, circulating tumor cell (CTC) isolation, plate changing and cell culturing. By using the present invention, time and labor are saved; moreover, the present invention has a small size and is easily carried.

Abstract: A chassis partition framework is provided for configuring a personal cluster computer that has a head-node mainboard, a first compute-node mainboard, a second compute-node mainboard, a third compute-node mainboard and a fourth compute-node mainboard. The chassis partition framework mainly includes a top chamber, a left chamber and a right chamber. The top chamber is for configuring the head-node mainboard horizontally. The left and right chambers located under the top chamber are for vertically configuring the first and second compute-node mainboards and the third and fourth compute-node mainboards respectively in face-to-face alignment, with the second and third compute-node mainboards standing in back-to-back alignment. Therefore, the mechanical problems of the conventional blade-type personal cluster computer about heat-dissipation, noise-reduction, expansibility and space-arrangement may be improved through the chassis partition framework.

Abstract: A structure of a semiconductor device including a substrate and a patterned layer is provided. The patterned layer being patterned to have an open area and a dense area is disposed on the substrate. The patterned layer includes, in the dense area, a first pattern adjacent to the open area and a second pattern. The first pattern has a first bottom. The second pattern has a second bottom width. The bottom of the first pattern includes a recess facing the open area, so that the first bottom width is close to the second bottom width.

Abstract: The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.

Abstract: A dual-board case for multi-mainboard system includes a rectangular-sectioned tubular housing, in which two track sets are provided; and two mainboard trays being movably mounted on the two track sets to locate at an interior of two opposite lateral walls of the tubular housing. Each of the two mainboard trays has a loading surface, on which a mainboard is mounted; and the two mainboard trays are mounted on the track sets with their loading surfaces and accordingly, the two mainboards mounted thereon facing toward each other. Therefore, the dual-board case allows a multi-mainboard system to have optimal spatial arrangement to achieve best heat-dissipation efficiency and largely reduce noises.

Abstract: A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O2 plasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The O2 plasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.

Abstract: A method for multi-step dielectric etching includes discharge steps between each of the etching steps in order to help release accumulated charge on the wafer produced by the previous etching step. The discharge steps stabilize the plasma discharge in each transition between etching steps. Charge elimination occurs because the negative species is relatively higher at the beginning of plasma spiking and can reach the wafer surface to reduce the accumulated charge.

Abstract: An openable dual-board case for multi-mainboard system includes a rectangular tubular body assembled from two bent plates connected together via a pivoting structure, so that the two bent plates are pivotally turnably about the pivoting structure relative to each other to open or close the tubular body. With the openable tubular body, necessary system assembling, dismounting, maintaining, and repairing can be conveniently and efficiently performed. Moreover, two mainboards may be separately mounted on two opposite interiors of the bent plates to face toward each other. Therefore, the openable dual-board case allows a multi-mainboard system to have optimal spatial arrangement to achieve best heat-dissipation efficiency and largely reduce noises.