Patents by Inventor Chun-I Tsai

Chun-I Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10777423
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
  • Publication number: 20200203222
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20200164439
    Abstract: A manufacturing method of a porous biomedical implant includes the steps of providing a supporter having a bearing surface, forming the porous biomedical implant on the bearing surface by additive manufacturing and removing the supporter after additive manufacturing. The porous biomedical implant includes a solid part and a porous part, the solid part is coupled to the bearing surface of the supporter and the porous part is coupled to the solid part. Particularly, the solid and porous parts are created in same layers by additive manufacturing.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 28, 2020
    Inventors: Meng-Hsiu Tsai, Tai-I Hsu, Chun-Chieh Wang, Chia-Min Wei
  • Publication number: 20200111739
    Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen CHENG, Wei-Yip LOH, Yu-Hsiang LIAO, Sheng-Hsuan LIN, Hong-Mao LEE, Chun-I TSAI, Ken-Yu CHANG, Wei-Jung LIN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20200075659
    Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jen-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Patent number: 10580693
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: March 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20200020578
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
  • Patent number: 10535697
    Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jen-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Patent number: 10504834
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20190273042
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 10361120
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20190201061
    Abstract: An expandable orthopedic implant includes a casing pipe, a shaft, a first expandable element and a first link lever. The casing pipe has a first opening, a second opening and an axis passing through the first and second opening. The casing pipe sheathes one end of the shaft, and the other end of the shaft has a top portion disposed out of the first opening. The first expandable element has a first terminal pivoted on the casing pipe and a second terminal. The first link lever has a proximal end pivoted to the top portion and a distal end pivoted to the second terminal. When the top portion is driven moving away from the first opening along an extending direction of the axis, the first link-lever can be pushed by the shaft to enact the second terminal moving away from the axis along a direction perpendicular to the axis.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, National Taiwan University Hospital
    Inventors: Pei-I TSAI, Hsin-Hsin SHEN, Kuo-Yi YANG, Shih-Ping LIN, Jui-Sheng SUN, Chih-Yu CHEN, Yu-Tsung CHIU, Chun-Ti CHEN, De-Yau LIN, An-Li CHEN
  • Publication number: 20190164824
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Application
    Filed: November 29, 2018
    Publication date: May 30, 2019
    Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20190164823
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Application
    Filed: January 25, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih WANG, Chun-I TSAI, Shian Wei MAO, Ken-Yu CHANG, Ming-Hsing TSAI, Wei-Jung LIN
  • Publication number: 20190157103
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Application
    Filed: June 8, 2018
    Publication date: May 23, 2019
    Inventors: TUNG-KAI CHEN, CHING-HSIANG TSAI, KAO-FENG LIAO, CHIH-CHIEH CHANG, CHUN-HAO KUNG, FANG-I CHIH, HSIN-YING HO, CHIA-JUNG HSU, HUI-CHI HUANG, KEI-WEI CHEN
  • Patent number: 10283359
    Abstract: Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Chun-I Tsai, Wei-Jung Lin, Huang-Yi Huang, Cheng-Tung Lin, Hong-Mao Lee
  • Patent number: 9978583
    Abstract: Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-I Tsai, Chi-Yuan Chen, Wei-Jung Lin, Chia-Han Lai
  • Publication number: 20170221710
    Abstract: Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Chun-I Tsai, Wei-Jung Lin, Huang-Yi Huang, Cheng-Tung Lin, Hong-Mao Lee
  • Publication number: 20170213720
    Abstract: Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening.
    Type: Application
    Filed: April 6, 2017
    Publication date: July 27, 2017
    Inventors: Chun-I Tsai, Chi-Yuan Chen, Wei-Jung Lin, Chia-Han Lai
  • Patent number: 9624576
    Abstract: Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Chun-I Tsai, Wei-Jung Lin, Huang-Yi Huang, Cheng-Tung Lin, Hong-Mao Lee