Patents by Inventor Chun-I Tsai
Chun-I Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220130755Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.Type: ApplicationFiled: January 3, 2022Publication date: April 28, 2022Inventors: SHUEN-SHIN LIANG, KEN-YU CHANG, HUNG-YI HUANG, CHIEN CHANG, CHI-HUNG CHUANG, KAI-YI CHU, CHUN-I TSAI, CHUN-HSIEN HUANG, CHIH-WEI CHANG, HSU-KAI CHANG, CHIA-HUNG CHU, KENG-CHU LIN, SUNG-LI WANG
-
Publication number: 20220084879Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.Type: ApplicationFiled: September 15, 2020Publication date: March 17, 2022Inventors: Pei-Wen WU, Chun-I TSAI, Chi-Cheng HUNG, Jyh-Cherng SHEU, Yu-Sheng WANG, Ming-Hsing TSAI
-
Patent number: 11217524Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.Type: GrantFiled: June 12, 2020Date of Patent: January 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shuen-Shin Liang, Ken-Yu Chang, Hung-Yi Huang, Chien Chang, Chi-Hung Chuang, Kai-Yi Chu, Chun-I Tsai, Chun-Hsien Huang, Chih-Wei Chang, Hsu-Kai Chang, Chia-Hung Chu, Keng-Chu Lin, Sung-Li Wang
-
Publication number: 20210391252Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Inventors: SHUEN-SHIN LIANG, KEN-YU CHANG, HUNG-YI HUANG, CHIEN CHANG, CHI-HUNG CHUANG, KAI-YI CHU, CHUN-I TSAI, CHUN-HSIEN HUANG, CHIH-WEI CHANG, HSU-KAI CHANG, CHIA-HUNG CHU, KENG-CHU LIN, SUNG-LI WANG
-
Patent number: 11195791Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.Type: GrantFiled: December 9, 2019Date of Patent: December 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
-
Publication number: 20210376103Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
-
Publication number: 20210343590Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
-
Publication number: 20210335720Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.Type: ApplicationFiled: January 5, 2021Publication date: October 28, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
-
Publication number: 20210225701Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
-
Patent number: 11062941Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: GrantFiled: March 2, 2020Date of Patent: July 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
-
Patent number: 10971396Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: GrantFiled: November 29, 2018Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
-
Publication number: 20200203222Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
-
Publication number: 20200111739Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Wen CHENG, Wei-Yip LOH, Yu-Hsiang LIAO, Sheng-Hsuan LIN, Hong-Mao LEE, Chun-I TSAI, Ken-Yu CHANG, Wei-Jung LIN, Chih-Wei CHANG, Ming-Hsing TSAI
-
Patent number: 10580693Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: GrantFiled: July 11, 2018Date of Patent: March 3, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
-
Publication number: 20200020578Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: ApplicationFiled: July 11, 2018Publication date: January 16, 2020Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
-
Patent number: 10504834Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.Type: GrantFiled: March 1, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
-
Publication number: 20190273042Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
-
Patent number: 10361120Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: GrantFiled: January 25, 2018Date of Patent: July 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
-
Publication number: 20190164823Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: ApplicationFiled: January 25, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Shih WANG, Chun-I TSAI, Shian Wei MAO, Ken-Yu CHANG, Ming-Hsing TSAI, Wei-Jung LIN
-
Publication number: 20190164824Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: ApplicationFiled: November 29, 2018Publication date: May 30, 2019Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin