Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

Abstract: A color conversion panel and a display device are provided. The color conversion panel includes an opaque substrate and a sapphire substrate. The opaque substrate includes a plurality of first pixel openings, a plurality of second pixel openings and a plurality of third pixel openings. The first pixel openings are filled with red quantum dot material, and the second pixel openings are filled with green quantum dot material. The sapphire substrate is on the opaque substrate. A first surface of the sapphire substrate that faces the opaque substrate has a plurality of first arc surfaces corresponding to the first pixel openings, a plurality of second arc surfaces corresponding to the second pixel openings, and a plurality of third arc surfaces corresponding to the third pixel openings.

Abstract: A display device and a projector are provided. The display device includes a pixel light-emitting panel and multiple color conversion panels. The pixel light-emitting panel includes an N1 number of light-emitting pixel units distributed in an array, and the light-emitting pixel units are driven to emit light through a driver. A first color conversion panel includes an N2 number of first color pixels and an N3 number of first transparent pixels. The first color pixels and the first transparent pixels are disposed relative to the light-emitting pixel units. A second color conversion panel includes an N4 number of second color pixels and an N5 number of second transparent pixels. The second color pixels and the second transparent pixels are disposed relative to the light-emitting pixel units. The lights generated by at least part of the light-emitting pixel units sequentially pass through the first color pixels and the second transparent pixels to achieve the color conversion.

Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.

Abstract: A light-emitting diode device includes an epitaxial structure that contains first-type and second-type semiconductor units and an active layer interposed therebetween, a light transmittable dielectric element that is disposed on the first-type semiconductor unit opposite to the active layer and is formed with a first through hole, an adhesive layer that is disposed on the dielectric element and is formed with a second through hole corresponding in position to the first through hole, and a metal contact element that is disposed on the adhesive layer. The adhesive layer has a thickness of at most one fifth of that of the dielectric element. The metal contact element extends into the first and second through holes, and electrically contacts the first-type semiconductor unit. A method for manufacturing the LED device is also disclosed.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: A semiconductor structure includes a plurality of semiconductor devices, each of which includes at least one channel layer, at least one interfacial layer, a gate dielectric layer, a gate electrode, and dipole elements. The at least one interfacial layer is disposed on the at least one channel layer. The gate dielectric layer is disposed over the at least one interfacial layer such that the at least one channel layer is separated from the gate dielectric layer through the at least one interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in the interfacial layer of at least one of the semiconductor devices in a predetermined amount such that the at least one of the semiconductor devices has a tunability of threshold voltage from that of the other of the semiconductor devices. Methods for manufacturing the semiconductor structure are also disclosed.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer includes an oxide material.

Abstract: An antenna structure includes a patch antenna including two opposite edges, a microstrip line connected to the patch antenna, two first radiation assemblies respectively disposed on two sides of the patch antenna, two second radiation assemblies disposed under the two first radiation assemblies, a liquid crystal layer disposed between a first plane and a second plane, and a ground plane disposed under the two second radiation assemblies. The patch antenna, the microstrip line, and the two first radiation assemblies are located on the first plane, and each of the first radiation assemblies includes multiple separated first conductors. The two second radiation assemblies are located on the second plane, and each of the second radiation assemblies includes multiple separated second conductors. A projection of the two second radiation assemblies on the first plane, the two first radiation assemblies, and the two edges of the patch antenna collectively form two loops.

Abstract: A method for measuring a physiological signal includes following steps: detecting a first physiological signal of a target; receiving the first physiological signal to generate a first signal and a second signal by a radar sensor; selecting one of the first signal and the second signal to generate a plurality of original signals, which a phase difference is formed between the first signal and the second signal; and capturing a respiration signal and a heartbeat signal according to the plurality of original signals.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate. The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer is thinner than the second metal-containing layer.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the silicon-containing layer, and the gate dielectric layer forming a gate stack.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: A method of manufacturing a device with a optical component disposed thereon, including following steps of: preparing a substrate, the substrate including a signal guide and an electric conductive structure; and mounting an optical component on the substrate and corresponding a light transmission face of the optical component to the signal guide, wherein the optical component and the substrate is connected by an adhesive material and the optical component is electrically connected with the electric conductive structure. A transmission device being made by the method of manufacturing the device with the optical component disposed thereon as described above is further provided.

Abstract: A light emitting diode structure includes a metal reflective layer, a first transparent electrically-conductive layer, a dielectric layer, second transparent electrically-conductive layers, a first type semiconductor layer, an active layer and a second type semiconductor layer. The metal reflective layer has first concave sections. The first transparent electrically-conductive layer is conformally formed over the first concave sections of the metal reflective layer. The dielectric layer is formed over the first transparent electrically-conductive layer and has through holes to expose the first transparent electrically-conductive layer. The second transparent electrically-conductive layers are formed over the dielectric layer, and connected with the first transparent electrically-conductive layer via the through holes. Each second transparent electrically-conductive layer is connected to the first transparent electrically-conductive layer to form a T-shaped cross section in each first concave section.

Abstract: A flip-chip light emitting device includes a substrate, a light-emitting layer, a bonding layer disposed between the substrate and the light-emitting layer, and a protective insulating layer disposed over the light-emitting layer and the bonding layer. The bonding layer has first and second upper surfaces that respectively have different first and second roughnesses.

Abstract: An antenna structure includes a patch antenna including two opposite edges, a microstrip line connected to the patch antenna, two first radiation assemblies respectively disposed on two sides of the patch antenna, two second radiation assemblies disposed under the two first radiation assemblies, a liquid crystal layer disposed between a first plane and a second plane, and a ground plane disposed under the two second radiation assemblies. The patch antenna, the microstrip line, and the two first radiation assemblies are located on the first plane, and each of the first radiation assemblies includes multiple separated first conductors. The two second radiation assemblies are located on the second plane, and each of the second radiation assemblies includes multiple separated second conductors. A projection of the two second radiation assemblies on the first plane, the two first radiation assemblies, and the two edges of the patch antenna collectively form two loops.

Abstract: A flip-chip light emitting device includes a transparent substrate, an epitaxial light-emitting structure, a transparent bonding layer interposed between the transparent substrate and the light-emitting structure, and a protective insulating layer disposed over the light-emitting structure and the bonding layer. The transparent bonding layer has a smaller-thickness section that has a first contact surface for the protective insulating layer to be disposed thereover, and a larger-thickness section that has a second contact surface meshing with and bonded to a roughened bottom surface of the light-emitting structure. The first contact surface is smaller in roughness than the second contact surface. A method for producing the device is also disclosed.