Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate. The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer is thinner than the second metal-containing layer.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: A light emitting diode includes an n-type confinement layer, a quantum well active layer formed on the n-type confinement layer, a p-type confinement layer formed on the quantum well active layer, a gallium phosphide-based quantum dot structure formed in the p-type confinement layer, and a GaP-based current spreading layer formed on the GaP-based quantum dot structure. A method of manufacturing the light emitting diode is also provided.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: Examples of a method of forming an integrated circuit device with an interfacial layer disposed between a channel region and a gate dielectric are provided herein. In some examples, the method includes receiving a workpiece having a substrate and a fin having a channel region disposed on the substrate. An interfacial layer is formed on the channel region of the fin, and a gate dielectric layer is formed on the interfacial layer. A first capping layer is formed on the gate dielectric layer, and a second capping layer is formed on the first capping layer. An annealing process is performed on the workpiece configured to cause a first material to diffuse from the first capping layer into the gate dielectric layer. The forming of the first and second capping layers and the annealing process may be performed in the same chamber of a fabrication tool.

Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.

Abstract: A flip-chip light emitting device includes a transparent substrate, an epitaxial light-emitting structure, a transparent bonding layer interposed between the transparent substrate and the light-emitting structure, and a protective insulating layer disposed over the light-emitting structure and the bonding layer. The transparent bonding layer has a smaller-thickness section that has a first contact surface for the protective insulating layer to be disposed thereover, and a larger-thickness section that has a second contact surface meshing with and bonded to a roughened bottom surface of the light-emitting structure. The first contact surface is smaller in roughness than the second contact surface. A method for producing the device is also disclosed.

Abstract: A light-emitting diode device includes an epitaxial structure that contains first-type and second-type semiconductor units and an active layer interposed therebetween, a light transmittable dielectric element that is disposed on the first-type semiconductor unit opposite to the active layer and is formed with a first through hole, an adhesive layer that is disposed on the dielectric element and is formed with a second through hole corresponding in position to the first through hole, and a metal contact element that is disposed on the adhesive layer. The adhesive layer has a thickness of at most one fifth of that of the dielectric element. The metal contact element extends into the first and second through holes, and electrically contacts the first-type semiconductor unit. A method for manufacturing the LED device is also disclosed.

Abstract: A light-emitting diode includes a PN junction light-emitting portion over a substrate; wherein the PN junction light-emitting portion includes an alternating-layer structure of alternating a strained light-emitting layer and a barrier layer, wherein the strained light-emitting layer with a component formula of GaXIn(1-x)AsY1P(1-Y), 0<X<1 and 0<Y?0.05, and the barrier layer has a component formula of (AlaGa1-A)bIn(1-b)P, 0.3?a?1 and 0<b<1; when a current of 350 mA flows through the PN junction light-emitting portion in forward direction, the light-emitting diode has an output power at least 202.2 mW.

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

Abstract: A light-emitting diode includes a PN junction light-emitting portion over a substrate; wherein the PN junction light-emitting portion includes an alternating-layer structure of alternating a strained light-emitting layer and a barrier layer, wherein the strained light-emitting layer with a component formula of GaXIn(1-X)AsY1P(1-Y), 0<X<1 and 0<Y?0.05, and the barrier layer has a component formula of (AlaGa1-A)bIn(1-b)P, 0.3?a?1 and 0<b<1; when a current of 350 mA flows through the PN junction light-emitting portion in forward direction, the light-emitting diode has an output power at least 202.2 mW.

Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.

Abstract: An epitaxial wafer for plant lighting light-emitting diodes (LED), the epitaxial wafer includes: a growth substrate; a first red-light epitaxial laminated layer; a distributed Bragg reflector (DBR) semiconductor laminated layer; and a second red-light epitaxial laminated layer; wherein: the first red-light epitaxial laminated layer comprises a first N-type ohmic contact layer, a first N-type covering layer, a first light-emitting layer, a first P-type covering layer, and a first P-type ohmic contact layer; and the second red-light epitaxial laminated layer comprises a second N-type ohmic contact layer, a second N-type covering layer, a second light-emitting layer, a second P-type covering layer, and a second P-type ohmic contact layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

Abstract: Examples of a method of forming an integrated circuit device with an interfacial layer disposed between a channel region and a gate dielectric are provided herein. In some examples, the method includes receiving a workpiece having a substrate and a fin having a channel region disposed on the substrate. An interfacial layer is formed on the channel region of the fin, and a gate dielectric layer is formed on the interfacial layer. A first capping layer is formed on the gate dielectric layer, and a second capping layer is formed on the first capping layer. An annealing process is performed on the workpiece configured to cause a first material to diffuse from the first capping layer into the gate dielectric layer. The forming of the first and second capping layers and the annealing process may be performed in the same chamber of a fabrication tool.

Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.

Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.

Abstract: A display panel includes waveguides, wires and a pixel array. The pixel array includes a plurality of pixel units. The pixel units are arranged in a plurality of columns and a plurality of rows. Each pixel unit includes a pixel electrode, a light filtering unit, and a photo transistor. The light filtering unit is coupled to one of the waveguides. The photo transistor is electrically connected to the pixel electrode and one of the wires, and is coupled to the light filtering unit. The waveguide transmits a light control signal. Each wire transmits an electric control signal. The light filtering unit is configured to receive a sub control signal from the waveguides to which the light filtering unit is coupled and filter out a specific optical signal according to the received sub control signal as an input signal of the photo transistor.

Abstract: An epitaxial wafer for plant lighting light-emitting diodes (LED), the epitaxial wafer includes: a growth substrate; a first red-light epitaxial laminated layer; a distributed Bragg reflector (DBR) semiconductor laminated layer; and a second red-light epitaxial laminated layer; wherein: the first red-light epitaxial laminated layer comprises a first N-type ohmic contact layer, a first N-type covering layer, a first light-emitting layer, a first P-type covering layer, and a first P-type ohmic contact layer; and the second red-light epitaxial laminated layer comprises a second N-type ohmic contact layer, a second N-type covering layer, a second light-emitting layer, a second P-type covering layer, and a second P-type ohmic contact layer.