Patents by Inventor Chun-Jen Chen
Chun-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11769833Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.Type: GrantFiled: September 30, 2022Date of Patent: September 26, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Patent number: 11756849Abstract: A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.Type: GrantFiled: June 8, 2022Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
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Publication number: 20230275047Abstract: A method includes forming a first polymer layer over a plurality of metal pads, and patterning the first polymer layer to forming a plurality of openings in the first polymer layer. The plurality of metal pads are exposed through the plurality of openings. A plurality of conductive vias are formed in the plurality of openings. A plurality of conductive pads are formed over and contacting the plurality of conductive vias. A conductive pad in the plurality of conductive pads is laterally shifted from a conductive via directly underlying, and in physical contact with, the conductive pad. A second polymer layer is formed to cover and in physical contact with the plurality of conductive pads.Type: ApplicationFiled: April 28, 2022Publication date: August 31, 2023Inventors: Chun-Jen Chen, Wei-Chun Pai, Cheng Wei Ho, Sheng-Huan Chiu
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Publication number: 20230245991Abstract: In an embodiment, a device includes: an integrated circuit die including a die connector; a dielectric layer on the integrated circuit die; an under-bump metallurgy layer having a line portion on the dielectric layer and having a via portion extending through the dielectric layer to contact the die connector; a through via on the line portion of the under-bump metallurgy layer, the through via having a first curved sidewall proximate the die connector, the through via having a second curved sidewall distal the die connector, the first curved sidewall having a longer arc length than the second curved sidewall; and an encapsulant around the through via and the under-bump metallurgy layer.Type: ApplicationFiled: May 12, 2022Publication date: August 3, 2023Inventors: Chun-Jen Chen, Wei-Chun Pai, Cheng Wei Ho, Sheng-Huan Chiu
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Publication number: 20230097129Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.Type: ApplicationFiled: December 1, 2022Publication date: March 30, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Publication number: 20230057327Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shih-Wen LU, Chun-Jen CHEN, Po-Hsiang TSENG, Hsin-Han LIN, Ming-Lun YU
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Patent number: 11587835Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, and forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature and a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.Type: GrantFiled: June 3, 2021Date of Patent: February 21, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin
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Publication number: 20230033820Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.Type: ApplicationFiled: September 30, 2022Publication date: February 2, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Patent number: 11545560Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.Type: GrantFiled: January 28, 2021Date of Patent: January 3, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Publication number: 20220398582Abstract: An information delivery method for transferring fund is provided. The information delivery method includes receiving payment information, determining whether a transfer condition is met according to the payment information, in response to determining that the transfer condition is met, obtaining source account information of a source entity and destination account information of a destination entity in the payment information, determining a transfer path according to the source account information of the source entity and the destination account information of the destination entity, and transmitting the payment information from the source entity to the destination entity according to the transfer path.Type: ApplicationFiled: June 11, 2021Publication date: December 15, 2022Applicant: OBOOK INC.Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chih-Yang Liu, Wei-Te Lin, I-Cheng Lin, Jun-De Liao, Kang-Hsien Chang, Chun-Jen Chen, Pei-Hsuan Weng, Yi-Hsuan Lai, Ming-Hung Lin, Shu-Ming Chang, Zih-Hao Lin
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Patent number: 11495686Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.Type: GrantFiled: January 13, 2021Date of Patent: November 8, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Patent number: 11488891Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate. The method includes depositing a first-side UBM layer on a first surface of the semiconductor substrate. The method includes forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the semiconductor substrate. The method includes forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.Type: GrantFiled: April 30, 2020Date of Patent: November 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: You-Hua Chou, Yi-Jen Lai, Chun-Jen Chen, Perre Kao
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Publication number: 20220301964Abstract: A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.Type: ApplicationFiled: June 8, 2022Publication date: September 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
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Patent number: 11404341Abstract: A package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The conductive structures include elliptical columns. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die and the conductive structures.Type: GrantFiled: February 24, 2020Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
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Publication number: 20220238457Abstract: A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.Type: ApplicationFiled: April 12, 2022Publication date: July 28, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hao-Chih HSIEH, Tzu-Cheng LIN, Chun-Jen CHEN
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Publication number: 20220190160Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.Type: ApplicationFiled: January 13, 2021Publication date: June 16, 2022Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Publication number: 20220181203Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Jen Chen, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
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Patent number: 11302646Abstract: A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.Type: GrantFiled: February 14, 2020Date of Patent: April 12, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hao-Chih Hsieh, Tzu-Cheng Lin, Chun-Jen Chen
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Patent number: 11264273Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: GrantFiled: July 28, 2020Date of Patent: March 1, 2022Inventors: Chun-Jen Chen, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
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Patent number: 11217548Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.Type: GrantFiled: December 13, 2018Date of Patent: January 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng