Patents by Inventor Chun-Jen Huang

Chun-Jen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240144868
    Abstract: The present disclosure provides a pixel circuit with pulse width compensation, and the pixel circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, and the pulse amplitude modulation circuit is electrically connected to the pulse width modulation circuit. The pulse width modulation circuit includes a P-type pulse width compensation transistor and a first P-type control transistor, and the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor. The pulse amplitude modulation circuit includes a second P-type control transistor, a first capacitor, a P-type driving transistor and a light-emitting element. The second P-type control transistor is electrically connected to the first P-type control transistor. The first capacitor is electrically connected to the second P-type control transistor.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Inventors: De-Fu CHEN, Po Lun CHEN, Chun-Ta CHEN, Ta-Jen HUANG, Po-Tsun LIU, Guang-Ting ZHENG, Ting-Yi YI
  • Publication number: 20240141108
    Abstract: Disclosed herein is a polysuccinimide derivative, which, under a pH of not greater than 6, includes a first repeating unit represented by formula (I), and a second repeating unit represented by formula (II), wherein each of the substituents is given the definition as set forth in the Specification and Claims. The second repeating unit is present in an amount ranging from 1 mol % to 90 mol % based on 100 mol % of the first repeating unit. Also disclosed herein is a nanomaterial including a plurality of nanoparticles, each of which, under a pH of not greater than 6, includes a hydrophobic substance and a carrier which is made from the polysuccinimide derivative and which encloses the hydrophobic substance.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventor: Chun-Jen HUANG
  • Publication number: 20240135897
    Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.
    Type: Application
    Filed: December 11, 2022
    Publication date: April 25, 2024
    Inventors: De-Fu CHEN, Po Lun CHEN, Chun-Ta CHEN, Ta-Jen HUANG, Po-Tsun LIU, Guang-Ting ZHENG, Ting-Yi YI
  • Publication number: 20240126002
    Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 18, 2024
    Applicant: Coretronic Corporation
    Inventors: Chih-Jen Tsang, Chung-Wei Huang, Shih-Yen Cheng, Jung-Wei Chang, Han-Yuan Liu, Chun-Wei Lee
  • Patent number: 11961489
    Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.
    Type: Grant
    Filed: December 11, 2022
    Date of Patent: April 16, 2024
    Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (ShenZhen) Co., Ltd., General Interface Solution Limited
    Inventors: De-Fu Chen, Po Lun Chen, Chun-Ta Chen, Ta-Jen Huang, Po-Tsun Liu, Guang-Ting Zheng, Ting-Yi Yi
  • Publication number: 20240096781
    Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.
    Type: Application
    Filed: March 20, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
  • Publication number: 20240071818
    Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.
    Type: Application
    Filed: September 22, 2022
    Publication date: February 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: I-Wei Chi, Te-Chang Hsu, Yao-Jhan Wang, Meng-Yun Wu, Chun-Jen Huang
  • Publication number: 20230352565
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 2, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang, Chun-Jen Huang
  • Patent number: 11742412
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: August 29, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang, Chun-Jen Huang
  • Publication number: 20220190735
    Abstract: A controlling method of a converter includes performing a state detecting step and a switch controlling step. The state detecting step is performed to detect an operation state of a secondary side rectifier of the converter from a control winding. The switch controlling step is performed to control an active clamp switch of the converter according to the operation state of the secondary side rectifier. The secondary side rectifier is a diode.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Inventors: Hsian-Pei YEE, Chun-Jen HUANG, Li-Min HUANG
  • Publication number: 20220069697
    Abstract: A controlling method of a converter including an active clamp switch and a secondary side rectifier includes performing a state detecting step and a switch controlling step. The state detecting step is performed to detect an operation state of the secondary side rectifier. The switch controlling step is performed to control the active clamp switch according to the operation state of the secondary side rectifier.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Inventors: Hsian-Pei YEE, Chun-Jen HUANG, Li-Min HUANG
  • Patent number: 11146266
    Abstract: A driving method and a driving device using the same are disclosed. The driving method controls a pulse transformer. The secondary winding of the pulse transformer is electrically connected to a control device. Firstly, positive charging electrical energy is delivered to the primary winding, thereby charging the control device. Then, the control device is disconnected from the secondary winding while the primary winding is in a high-impedance state. Finally, negative discharging electrical energy is delivered to the primary winding and the control device is electrically connected to the secondary winding, thereby discharging the control device, and the primary winding is in a low-impedance state after the step of delivering the negative discharging electrical energy to the primary winding.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: October 12, 2021
    Assignee: SYNC POWER CORP.
    Inventors: Hsian-Pei Yee, Chun-Jen Huang
  • Publication number: 20210171688
    Abstract: A biocompatible copolymer includes a phosphorylcholine-containing structural unit represented by formula (I), a siloxy-containing structural unit represented by formula (II), and a photoreactive structural unit represented by formula (III), wherein each of the substituents is given the definition as set forth in the Specification and Claims. A curable composition, a biocompatible coating layer, and a biocompatible device containing the biocompatible copolymer are also disclosed.
    Type: Application
    Filed: October 26, 2020
    Publication date: June 10, 2021
    Inventors: Chun-Jen HUANG, Jin-He KE
  • Publication number: 20210152173
    Abstract: A driving method and a driving device using the same are disclosed. The driving method controls a pulse transformer. The secondary winding of the pulse transformer is electrically connected to a control device. Firstly, positive charging electrical energy is delivered to the primary winding, thereby charging the control device. Then, the control device is disconnected from the secondary winding while the primary winding is in a high-impedance state. Finally, negative discharging electrical energy is delivered to the primary winding and the control device is electrically connected to the secondary winding, thereby discharging the control device, and the primary winding is in a low-impedance state after the step of delivering the negative discharging electrical energy to the primary winding.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 20, 2021
    Inventors: Hsian-Pei YEE, Chun-Jen HUANG
  • Patent number: 10957762
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 23, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Patent number: 10892365
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Patent number: 10875023
    Abstract: An oriented loading system is provided. The oriented loading system includes a substrate, a plurality of wells formed in the substrate, each well having a bottom and sidewalls, a plurality of particles loaded in the wells, wherein the particle comprises a core structure and an inner layer comprising magnetic material partially covering the core structure such that a part of the core structure uncovered by the inner layer is exposed, and a metal layer comprising magnetic material deposited partially in the sidewalls of the wells, wherein the inner layer is attracted by the metal layer such that the exposed core structure is oriented towards the bottom of the well or the inner layer is oriented towards the bottom of the well.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: December 29, 2020
    Assignee: PERSONAL GENOMICS, INC.
    Inventors: Ching-Wei Tsai, Hsin-Yi Hsieh, Yu-Hsuan Peng, Wen-Yih Chen, Chun-Jen Huang
  • Publication number: 20200365710
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 19, 2020
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang, Chun-Jen Huang
  • Patent number: 10777657
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang, Chun-Jen Huang
  • Publication number: 20200279917
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang