Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.

Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: A method for CMP includes following operations. A first metal layer and a second metal layer are formed in a dielectric structure. The second metal layer is formed over a portion of the first metal layer. A first composition is provided to remove a portion of the first metal layer. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed to expose the second metal layer. A CMP operation is performed to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure.

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, an anisotropic layer on the first buffer layer, a second buffer layer on the first buffer layer, and a bulk layer on the anisotropic layer. Preferably, a concentration of boron in the bulk layer is less than a concentration of boron in the anisotropic layer, a concentration of boron in the first buffer layer is less than a concentration of boron in the second buffer layer, and the concentration of boron in the second buffer layer is less than the concentration of boron in the anisotropic layer.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.

Abstract: Disclosed herein is a polysuccinimide derivative, which, under a pH of not greater than 6, includes a first repeating unit represented by formula (I), and a second repeating unit represented by formula (II), wherein each of the substituents is given the definition as set forth in the Specification and Claims. The second repeating unit is present in an amount ranging from 1 mol % to 90 mol % based on 100 mol % of the first repeating unit. Also disclosed herein is a nanomaterial including a plurality of nanoparticles, each of which, under a pH of not greater than 6, includes a hydrophobic substance and a carrier which is made from the polysuccinimide derivative and which encloses the hydrophobic substance.

Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

Abstract: A controlling method of a converter includes performing a state detecting step and a switch controlling step. The state detecting step is performed to detect an operation state of a secondary side rectifier of the converter from a control winding. The switch controlling step is performed to control an active clamp switch of the converter according to the operation state of the secondary side rectifier. The secondary side rectifier is a diode.

Abstract: A controlling method of a converter including an active clamp switch and a secondary side rectifier includes performing a state detecting step and a switch controlling step. The state detecting step is performed to detect an operation state of the secondary side rectifier. The switch controlling step is performed to control the active clamp switch according to the operation state of the secondary side rectifier.

Abstract: A driving method and a driving device using the same are disclosed. The driving method controls a pulse transformer. The secondary winding of the pulse transformer is electrically connected to a control device. Firstly, positive charging electrical energy is delivered to the primary winding, thereby charging the control device. Then, the control device is disconnected from the secondary winding while the primary winding is in a high-impedance state. Finally, negative discharging electrical energy is delivered to the primary winding and the control device is electrically connected to the secondary winding, thereby discharging the control device, and the primary winding is in a low-impedance state after the step of delivering the negative discharging electrical energy to the primary winding.

Abstract: A biocompatible copolymer includes a phosphorylcholine-containing structural unit represented by formula (I), a siloxy-containing structural unit represented by formula (II), and a photoreactive structural unit represented by formula (III), wherein each of the substituents is given the definition as set forth in the Specification and Claims. A curable composition, a biocompatible coating layer, and a biocompatible device containing the biocompatible copolymer are also disclosed.

Abstract: A driving method and a driving device using the same are disclosed. The driving method controls a pulse transformer. The secondary winding of the pulse transformer is electrically connected to a control device. Firstly, positive charging electrical energy is delivered to the primary winding, thereby charging the control device. Then, the control device is disconnected from the secondary winding while the primary winding is in a high-impedance state. Finally, negative discharging electrical energy is delivered to the primary winding and the control device is electrically connected to the secondary winding, thereby discharging the control device, and the primary winding is in a low-impedance state after the step of delivering the negative discharging electrical energy to the primary winding.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.

Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.

Abstract: An oriented loading system is provided. The oriented loading system includes a substrate, a plurality of wells formed in the substrate, each well having a bottom and sidewalls, a plurality of particles loaded in the wells, wherein the particle comprises a core structure and an inner layer comprising magnetic material partially covering the core structure such that a part of the core structure uncovered by the inner layer is exposed, and a metal layer comprising magnetic material deposited partially in the sidewalls of the wells, wherein the inner layer is attracted by the metal layer such that the exposed core structure is oriented towards the bottom of the well or the inner layer is oriented towards the bottom of the well.