Patents by Inventor Chun-Jen Huang
Chun-Jen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100258941Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.Type: ApplicationFiled: June 23, 2010Publication date: October 14, 2010Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Patent number: 7767578Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.Type: GrantFiled: January 11, 2007Date of Patent: August 3, 2010Assignee: United Microelectronics Corp.Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Patent number: 7692960Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.Type: GrantFiled: December 20, 2006Date of Patent: April 6, 2010Assignee: Macronix International Co., Ltd.Inventors: Chang-Ting Chen, Chun-Jen Huang
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Patent number: 7628866Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.Type: GrantFiled: November 23, 2006Date of Patent: December 8, 2009Assignee: United Microelectronics Corp.Inventors: Miao-Chun Lin, Cheng-Ming Weng, Chun-Jen Huang
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Patent number: 7539058Abstract: A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit and a synchronous programming circuit. The memory cell array includes a first memory cell, and the first dummy cell array includes a first dummy cell. The first dummy cell is adjacent to a first side of a memory cell array and corresponds to the first memory cell. The address decoding unit receives an address signal for decoding. When the address signal is a relative address of the first dummy cell, the synchronous programming circuit controls the first dummy cell and the first memory cell to be synchronously programmed.Type: GrantFiled: July 17, 2007Date of Patent: May 26, 2009Assignee: Macronix International Co., Ltd.Inventors: Chun-Jen Huang, Chia-Jung Chen, Hsin-Yi Ho
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Patent number: 7524742Abstract: A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.Type: GrantFiled: May 14, 2007Date of Patent: April 28, 2009Assignee: United Microelectronics Corp.Inventors: Pei-Yu Chou, Chun-Jen Huang
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Publication number: 20090021980Abstract: A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit and a synchronous programming circuit. The memory cell array includes a first memory cell, and the first dummy cell array includes a first dummy cell. The first dummy cell is adjacent to a first side of a memory cell array and corresponds to the first memory cell. The address decoding unit receives an address signal for decoding. When the address signal is a relative address of the first dummy cell, the synchronous programming circuit controls the first dummy cell and the first memory cell to be synchronously programmed.Type: ApplicationFiled: July 17, 2007Publication date: January 22, 2009Applicant: Macronix International Co., Ltd.Inventors: Chun-Jen Huang, Chia-Jung Chen, Hsin-Yi Ho
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Patent number: 7474565Abstract: An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.Type: GrantFiled: December 11, 2006Date of Patent: January 6, 2009Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Jen Huang, Chia-Jung Chen, Hsin-Yi Ho
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Publication number: 20080171433Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Patent number: 7397705Abstract: A method for operating a charge-trapping multi-level cell (“MLC”) memory array comprises programming a first plurality of charge-trapping sites to a preliminary first-level value, programming a second plurality of charge-trapping sites to a preliminary second-level value, and programming a third plurality of charge-trapping sites to a final third-level value using a first programming scheme. Then, the first plurality of charge-trapping sites is programmed to a final first-level value and the second plurality of charge-trapping sites is programmed to a final second-level value using a second programming scheme.Type: GrantFiled: February 1, 2007Date of Patent: July 8, 2008Assignee: Macronix International Co., Ltd.Inventors: Chun Jen Huang, Chung Kuang Chen, Hsin Yi Ho
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Publication number: 20080151620Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chang-Ting Chen, Chun-Jen Huang
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Publication number: 20080153243Abstract: Blanket implant diode which can be used for transient voltage suppression having a P+ substrate implanted with an N-type dopant blanket implant near a top surface of the substrate, creating a P? region. An oxide mask is layered adjacent to and above the P? region. The oxide mask is partially etched away from a portion of the P? region, creating an etched region. An N-type main function implant is implanted into the etched region, creating an N+ region above the P+ substrate and adjacent the P? region. And, a metal is layered above the oxide mask in the etched region to form an electrode. Terminations may be attached electrically to both sides of the P-N junction. Methods of making and using the present invention and methods for transient voltage suppression are also provided.Type: ApplicationFiled: February 20, 2008Publication date: June 26, 2008Applicant: VISHAY GENERAL SEMICONDUCTORS, LLCInventors: SHENG-HUEI DAI, YA-CHIN KING, CHUN-JEN HUANG, L.C. KAO
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Publication number: 20080146036Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.Type: ApplicationFiled: December 18, 2006Publication date: June 19, 2008Inventors: Yu-Tsung Lai, Chun-Jen Huang, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20080137427Abstract: An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.Type: ApplicationFiled: December 11, 2006Publication date: June 12, 2008Inventors: Chun-Jen Huang, Chia-Jung Chen, Hsin-Yi Ho
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Publication number: 20080121619Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.Type: ApplicationFiled: November 23, 2006Publication date: May 29, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Miao-Chun Lin, Cheng-Ming Weng, Chun-Jen Huang
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Patent number: 7378343Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.Type: GrantFiled: November 17, 2005Date of Patent: May 27, 2008Assignee: United Microelectronics Corp.Inventors: Jei-Ming Chen, Miao-Chun Lin, Kuo-Chih Lai, Mei-Ling Chen, Cheng-Ming Weng, Chun-Jen Huang, Yu-Tsung Lai
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Patent number: 7365009Abstract: A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.Type: GrantFiled: January 4, 2006Date of Patent: April 29, 2008Assignee: United Microelectronics Corp.Inventors: Pei-Yu Chou, Chun-Jen Huang
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Publication number: 20070249165Abstract: A dual damascene process is provided. A substrate having a conductive area is provided. An etching stop layer, a dielectric layer and a patterned hard mask layer are sequentially formed on the substrate. A first opening is formed in the dielectric layer exposed by the patterned hard mask layer. A first material layer having a high etching selectivity with respect to the dielectric layer is deposited to fill the first opening. A portion of the dielectric layer and the filling material layer are removed to form a trench and a second opening. The filling material layer exposed by the second opening is removed to expose part of the etching stop layer. A portion of the etching stop layer is removed to form a third opening. A conductive layer is formed in the trench and the third opening.Type: ApplicationFiled: April 5, 2006Publication date: October 25, 2007Inventors: Chun-Jen Huang, Cheng-Ming Weng, Meng-Jun Wang
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Publication number: 20070210454Abstract: A process and structure for a metal interconnect comprises providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.Type: ApplicationFiled: May 14, 2007Publication date: September 13, 2007Inventors: Pei-Yu Chou, Chun-Jen Huang
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Publication number: 20070155157Abstract: A process and structure for a metal interconnect comprises providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.Type: ApplicationFiled: January 4, 2006Publication date: July 5, 2007Inventors: Pei-Yu Chou, Chun-Jen Huang