Patents by Inventor Chun-Jen Huang

Chun-Jen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160261527
    Abstract: An instant messaging system is configured to facilitate digital photo sharing. An invitation is transmitted to at least one contact at a corresponding instant messaging system, where the invitation includes a selected digital photo presentation template comprising a plurality of panels. Digital photos are uploaded to a media content server, and digital photos shared by the at least one invited contact are accessed, where the digital photos are arranged in each of the panels of the presentation template according to at least one viewing criterion specified by a user of the instant messaging system.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 8, 2016
    Inventor: CHUN JEN HUANG
  • Publication number: 20160193602
    Abstract: An oriented loading system is provided. The oriented loading system includes a substrate, a plurality of wells formed in the substrate, each well having a bottom and sidewalls, a plurality of particles loaded in the wells, wherein the particle comprises a core structure and an inner layer comprising magnetic material partially covering the core structure such that a part of the core structure uncovered by the inner layer is exposed, and a metal layer comprising magnetic material deposited partially in the sidewalls of the wells, wherein the inner layer is attracted by the metal layer such that the exposed core structure is oriented towards the bottom of the well or the inner layer is oriented towards the bottom of the well.
    Type: Application
    Filed: January 6, 2016
    Publication date: July 7, 2016
    Applicant: PERSONAL GENOMICS, INC.
    Inventors: Ching-Wei TSAI, Hsin-Yi HSIEH, Yu-Hsuan PENG, Wen-Yih CHEN, Chun-Jen HUANG
  • Publication number: 20160194218
    Abstract: The present disclosure provides an oil-water separation porous structure including a substrate and an oil-water separation material layer. The substrate has a plurality of pores. The oil-water separation material layer is disposed on a surface of the substrate, which includes a zwitterionic molecule including an organosilane group and a zwitterionic group. A method for manufacturing the oil-water separation porous structure and an oil-water separation device having the oil-water separation porous structure are also disclosed herein.
    Type: Application
    Filed: March 3, 2015
    Publication date: July 7, 2016
    Inventor: Chun-Jen HUANG
  • Patent number: 9214859
    Abstract: In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: December 15, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Yung Feng Lin, Chun-Jen Huang, Tzeng-Huei Shiau, Chun-Hsiung Hung, Caiyun Wu, Qifang Wang
  • Patent number: 9106146
    Abstract: An energy-saving control device is disclosed. The control device is connected with an integrated circuit (IC) and a secondary winding of a transformer of a power converter. A primary winding of the transformer receives energy, and then the energy is discharged from the secondary winding and an energy signal of the energy is generated. And the energy signal comprises a high-frequency part and a low-frequency part thereafter. The energy signal is received by the energy-saving control device to control the operation of the IC according to a ratio of the low-frequency part to the high-frequency part.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 11, 2015
    Assignee: SYNC POWER CORPORATION
    Inventors: Hsian-Pei Yee, Chun-Jen Huang
  • Publication number: 20140268916
    Abstract: An energy-saving control device is disclosed. The control device is connected with an integrated circuit (IC) and a secondary winding of a transformer of a power converter. A primary winding of the transformer receives energy, and then the energy is discharged from the secondary winding and an energy signal of the energy is generated. And the energy signal comprises a high-frequency part and a low-frequency part thereafter. The energy signal is received by the energy-saving control device to control the operation of the IC according to a ratio of the low-frequency part to the high-frequency part.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: SYNC POWER CORPORATION
    Inventors: Hsian-Pei YEE, Chun-Jen HUANG
  • Patent number: 8736362
    Abstract: A beat frequency cancellation circuit, for an amplifier, includes a coupling device connected between two signal processing paths of the amplifier for compensating for beat frequency effects of output signals between the signal processing paths.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: May 27, 2014
    Assignee: Princeton Technology Corporation
    Inventors: Chun-Jen Huang, Jiann-Chyi Rau, Hsin-Hung Wang
  • Publication number: 20130285737
    Abstract: In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: Macronix International Co., Ltd.
    Inventors: Yung Feng Lin, Chun-Jen Huang, Tzeng-Huei Shiau, Chun-Hsiung Hung, Caiyun Wu, Qifang Wang
  • Publication number: 20130244249
    Abstract: Hierarchical films with structurally regulated functionalities through the integration of two-dimensional and three-dimensional structures to achieve ultra low nonspecific binding and high loading of molecular recognition elements, and methods for making and using the films.
    Type: Application
    Filed: January 22, 2013
    Publication date: September 19, 2013
    Inventors: Shaoyi Jiang, Norman David Brault, JR., Harihara S. Sundaram, Chun-Jen Huang, Qiuming Yu, Yuting Li
  • Patent number: 8269548
    Abstract: General speaking, a resistor of high resistivity has a negative-temperature-coefficient and a resistor of low resistivity has a positive-temperature-coefficient. Utilizing this characteristic, an appropriate proportion between the above resistors can be found to make a combined resistor with an approximate zero-temperature-coefficient. The combined resistor can be used to design a circuit for generating voltage and current with approximate zero-temperature-coefficients.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: September 18, 2012
    Assignee: Princeton Technology Corporation
    Inventor: Chun-Jen Huang
  • Publication number: 20120229207
    Abstract: A beat frequency cancellation circuit, for an amplifier, includes a coupling device connected between two signal processing paths of the amplifier for compensating for beat frequency effects of output signals between the signal processing paths.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 13, 2012
    Applicant: PRINCETON TECHNOLOGY CORPORATION
    Inventors: Chun-Jen HUANG, Jiann-Chyi RAU, Hsin-Hung WANG
  • Publication number: 20120061840
    Abstract: A dual damascene structure is disclosed. The dual damascene structure includes: a substrate comprising thereon a base dielectric layer and a lower wiring layer inlaid in the base dielectric layer; a dielectric layer on the substrate; a via opening in the dielectric layer, wherein the via opening misaligns with the lower wiring layer thus exposing a portion of the lower wiring layer and a portion of the base dielectric layer, wherein the via opening comprises a bottom including a recessed area; a barrier layer lining interior surface of the via opening and covers the exposed lower wiring layer and the base dielectric layer, wherein only the barrier layer fills the recessed area; and a copper layer filling the via opening on the barrier layer.
    Type: Application
    Filed: November 17, 2011
    Publication date: March 15, 2012
    Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Patent number: 8080877
    Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: December 20, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Publication number: 20110248747
    Abstract: General speaking, a resistor of high resistivity has a negative-temperature-coefficient and a resistor of low resistivity has a positive-temperature-coefficient. Utilizing this characteristic, an appropriate proportion between the above resistors can be found to make a combined resistor with an approximate zero-temperature-coefficient. The combined resistor can be used to design a circuit for generating voltage and current with approximate zero-temperature-coefficients.
    Type: Application
    Filed: April 6, 2011
    Publication date: October 13, 2011
    Inventor: Chun-Jen Huang
  • Patent number: 7977244
    Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: July 12, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Tsung Lai, Chun-Jen Huang, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Publication number: 20100258941
    Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
    Type: Application
    Filed: June 23, 2010
    Publication date: October 14, 2010
    Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Patent number: 7767578
    Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: August 3, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Patent number: 7692960
    Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: April 6, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Chang-Ting Chen, Chun-Jen Huang
  • Patent number: 7628866
    Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.
    Type: Grant
    Filed: November 23, 2006
    Date of Patent: December 8, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Miao-Chun Lin, Cheng-Ming Weng, Chun-Jen Huang
  • Patent number: 7539058
    Abstract: A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit and a synchronous programming circuit. The memory cell array includes a first memory cell, and the first dummy cell array includes a first dummy cell. The first dummy cell is adjacent to a first side of a memory cell array and corresponds to the first memory cell. The address decoding unit receives an address signal for decoding. When the address signal is a relative address of the first dummy cell, the synchronous programming circuit controls the first dummy cell and the first memory cell to be synchronously programmed.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: May 26, 2009
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Jen Huang, Chia-Jung Chen, Hsin-Yi Ho