Abstract: A diode is comprised of a doped region formed with a first dopant of a first conductivity type. In addition, the diode further comprises a substrate doped with a second dopant of a second conductivity type opposite of the first conductivity type. The lightly doped substrate, instead of a well, abuts the doped region for minimizing a junction capacitance of the diode. Such a diode is especially advantageous for ESD (electro-static discharge) protection of high speed integrated circuits.

Abstract: A zero power memory cell includes first and second NMOS transistors and a PMOS transistor, wherein the first NMOS transistor and first PMOS transistor each include a three-implant channel region, and wherein the second NMOS transistor further includes a two-implant channel region.

Abstract: A method for forming a uniformly planarized structured in a semiconductor wafer forms metal structures on a substrate layer with spaces between the structures. The top surfaces of the metal structures lie within a common plane. Dielectric material is deposited on the layer, the metal structures and in the spaces. The dielectric layer is first etched so that the dielectric material in the spaces is below the common plane. Additional dielectric material is then deposited on the layer, the metal structures and in the spaces. The dielectric layer is then subjected to a second etching. Further deposition and etching steps are performed until the top of the dielectric layer and the top surfaces of the metal structures have a common, substantially uniform planarization.

Abstract: A method for forming a three transistor zero power memory cell including a p-channel sense transistor, an n-channel write transistor, and an n-channel sense transistor including: implanting a p-type impurity into a p-type substrate in which a n-channel high voltage transistor will be formed; implanting an n-type impurity into an n-type well in a p-type substrate in which a p-channel high voltage transistor will be formed; forming a mask to allow implants to occur to p-channel devices; performing a series of n-type dopant implants into the substrate where the p-channel transistors will be formed; growing a high voltage gate oxide; forming a mask to allow implants to occur to n-channel devices, said mask blocking implants to said n-channel sense transistor; and performing a series of p-type implants into the substrate where the n-channel devices will be formed. In addition, a memory cell which may include a first NMOS transistor having a source, drain and gate, and a first PMOS transistor is disclosed.

Abstract: An EEPROM device having improved data retention and process for fabricating the device includes a two-step deposition process for the fabrication of an ILD layer overlying the high voltage elements of an EEPROM memory cell. The ILD layer is fabricated by first depositing an insulating layer on a high voltage device layer and thermally treating insulating layer. A second insulating layer is then deposited to overlie the first insulating layer. An EEPROM device in accordance with the invention includes a floating-gate transistor having a specified threshold voltage. A thermally-treated, boron-doped oxide layer overlies the floating-gate transistor and a second oxide layer overlies the thermally-treated, boron-doped oxide layer. The memory device exhibits data retention characteristics, such that upon subjecting the device to a baked temperature of at least about 250° C. for at least about 360 hours, the threshold voltage of the floating-gate transistor shifts by no more than about 100 mV.

Abstract: The present invention relates to a device and a method for connecting a mobile phone handset to an external keyboard. A multimedia card slot interface is included in the portable keyboard of the present invention, which can be incorporated to the original interface of the handset. In the meantime, a microprocessor and a random access memory are also included in the keyboard. After sending an interrupt command from the handset to the keyboard, by scanning the keyboard, whether the key is pressed or not is determined by the microprocessor and the key value is stored in its own random access memory. When the key value is stored in the random access memory, an interrupt command is sent to the handset by the keyboard. After the handset is ready, the key value will be transferred to the handset via the multimedia card slot interface.

Abstract: An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. P-type lightly-doped drain regions are located at the polysilicon edges of the tunnel window. During the programming operation, the P-type lightly-doped drain regions are in contacting with the polysilicon edges. As a result, there is reduced or suppressed the tunneling current to the program junction region so as to improve the efficiency of programming.

Abstract: The capacitance between the gate of a transistor and local interconnect is reduced employing SiC as an etch stop layer. Embodiments include depositing a SiC etch stop layer having a thickness of about 500-1000 Å and a dielectric constant of less than about 3.2, thereby providing a composite dielectric constant between the gate and local interconnect of between about 3.7 to about 4.7. The SiC etch stop layer can be deposited by PECVD or HDP techniques.

Abstract: An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P+ implant is provided at the tunnel window edge. During the programming operation, the P+ contacted inversion layer is used instead of the program junction. As a result, there is eliminated the voltage drop in the program junction region so as to improve the efficiency of programming.

Abstract: An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P+ implant is provided at the tunnel window edge. During the programming operation, the P+ contacted inversion layer is used instead of the program junction. As a result, there is eliminated the voltage drop in the program junction region so as to improve the efficiency of programming.

Abstract: Air gap insulation regions are formed selectively within high parasitic capacitance regions in which conductive lines are closely proximate and generates an intolerable amount of parasitic capacitance. The selective formation of air gap insulation regions improves circuit performance by reducing the parasitic capacitance and device reliability by reducing the stress fracture problem of conventional air gap insulation schemes.

Abstract: A Chinese-character input method and system is provided to allow users to input Chinese characters to a data processor with a reduced keyboard, such as a mobile-phone handset with a CCITT-compliant (Consultative Committee in International Telegraphy and Telephony) keyboard having only 12 keys. This Chinese-character input method and system allows the user to input Chinese characters to the data processor through a plurality of virtual keyboards which collectively display a set of phonetic symbols, such as those in the Mandarin Phonetic Symbol Set or the Roman Symbol Set, so that the user can perform the input operation through a pronunciation-based input scheme. The Chinese-character input method and system arranges the virtual keyboards in relational layers in accordance with the Mandarin Phonetic-Symbol Combination Rules or the Chinese Roman-Symbol Combination Rules, so that the user can perform the task of Chinese-character input to the data processor more conveniently and efficiently than the prior art.

Abstract: The invention provides a method and apparatus for calculating gate length and source/drain gate overlap, by measuring gate capacitance. The invention uses previously known fringe capacitance C.sub.fr and unit capacitance C.sub.OX. The invention measures gate capacitance C.sub.g, when the gate is accumulatively biased, and solves for overlap capacitance C.sub.OV using the equation C.sub.OV =(C.sub.g -2C.sub.fr)/2 or C.sub.OV =(C.sub.gg -C.sub.gb -2C.sub.fr)/2. The invention then measures the gate capacitance C.sub.g when the gate to source/drain voltage is set to inversion bias and a zero voltage is applied between the source/drain and the substrate, and solves for the channel capacitance C.sub.ch using the equation C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV. The invention calculates the channel capacitance C.sub.ch where C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV and then calculates gate length where gate length L.sub.g =(2C.sub.OV +C.sub.ch)/C.sub.OX and the effective gate length L.sub.eff =C.sub.ch /C.sub.OX.

Abstract: The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 .ANG. to about 800 .ANG. having a dielectric constant of less than about 3.2, depositing a silicon oxide inter-dielectric layer, and forming the local interconnect through the inter-dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.

Abstract: When simulating a circuit's behavior, a transistor can be modeled to account for gate resistance induced propagation delay. In one embodiment, the model includes a transistor with a resistor connected to the gate of the transistor. The resistor has a resistance equal to one third of the gate resistance.

Abstract: A system for simplifying and expediting estimation of the gate RC delay and/or the determination of transistor widths for a given gate RC delay in a CMOS inverter circuit. The system determines gate RC delay as a function of transistor width. Alternatively, appropriate transistor widths may be determined based on a desired optimum gate RC delay. An analytical expression is established to predict RC induced gate propagation delay as a function of readily available technical parameters in the early stage of design. The analytical expression has been found to describe gate RC delay in CMOS inverter circuits incorporating 0.25 micron (or even smaller) manufacturing technology.

Abstract: A method and apparatus that uses gate-to-substrate capacitance with varying amounts of source/drain junction bias to measure channel lateral doping profile by applying a series of different voltages between the source/drain and the substrate. The gate capacitance is measured for the different voltages. The capacitance is used to calculate the depletion width. From the depletion width, channel doping is calculated. Using this method direct evidence of a localized Boron pile up at source/drain edge is shown.

Abstract: A system and method for providing a plurality of interconnects for a microcircuit is disclosed. The microcircuit has a plurality of functional components. The method and system include determining the placement of each of the plurality of functional components and determining a width of each of the plurality of interconnects. The determination of the width is based on a capacitance between each interconnect and a portion of the plurality of interconnects.

Abstract: A method of making a transistor is also disclosed, including the steps of forming a gate oxide layer (106) over a semiconductor substrate (100) and forming a gate structure (108) over a portion of the gate oxide layer (106), thereby separating the transistor into a first region (114) and a second region (112) with a channel region therebetween. The method also includes forming a source region (114) having a source LDD portion (116) and forming a drain region (112) having a drain LDD portion (124) in the second region (112), wherein the drain LDD portion (124) is more shallow than the source LDD portion (1 16). An asymmetric source/drain LDD transistor structure includes a semiconductor substrate (100), a gate oxide layer (106) overlying the substrate (100) and a gate structure (108) overlying the gate oxide layer (106).

Abstract: A structure is used for electrostatic discharge protection of an integrated circuit. The modified ladder structure includes drain regions which extend from an output pad. These are interleaved with source regions. For example, for a structure with two drain regions and two source regions, a first drain region extending from the output pad is separated from a first source region by a first gate region. A second drain region extending from the output pad is separated from the first drain region by a first insulating region. A second source region is separated from the second drain region by a second gate structure. For a structure with four drain regions and three source regions, there is additionally, a third drain region extending from the output pad. The third drain region is separated from the second source region by a third gate region. A fourth drain region extending from the output pad is separated from the third drain region by a second insulating region.