Patents by Inventor Chun Liu

Chun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240069606
    Abstract: A portable electronic device including a first body, a second body, and a hinge mechanism is provided. The second body is connected to the first body through the hinge mechanism, and the hinge mechanism has a basis axis located at the first body and a rotation axis located at a lower end of the second body. When the second body rotates with respect to the first body, the rotation axis slides along an arc shaped path with respect to the basis axis to increase or decrease a distance between the rotation axis and the basis axis and increase or decrease a distance between the lower end of the second body and a back end of the first body.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 29, 2024
    Applicants: Acer Incorporated, Sinher Technology Inc.
    Inventors: Yi-Ta Huang, Cheng-Nan Ling, Chih-Chun Liu, Yung-Chang Chiang
  • Publication number: 20240067746
    Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 29, 2024
    Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
  • Publication number: 20240071854
    Abstract: Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Wen-Yi LIN, Kuang-Chun LEE, Chien-Chen LI, Chien-Li KUO, Kuo-Chio LIU
  • Publication number: 20240068119
    Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.
    Type: Application
    Filed: March 2, 2023
    Publication date: February 29, 2024
    Applicant: Acer Incorporated
    Inventors: Tzu-Wei Lin, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
  • Publication number: 20240072459
    Abstract: An electrical connection structure including a first substrate, a first conductive pad, a second substrate, a second conductive pad, at least two through holes and a conductive material. The first conductive pad is disposed on the first substrate and includes a first top surface. The second conductive pad is disposed on the second substrate and includes a second top surface. The at least two through holes pass through the first substrate and expose portions of the second top surface. A portion of the conductive material is disposed within the at least two through holes, and the conductive material electrically connects the first conductive pad and the second conductive pad.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 29, 2024
    Applicant: InnoLux Corporation
    Inventors: Chia-Chun LIU, Hao-Jung HUANG
  • Publication number: 20240071504
    Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Chun LIAO, Yu-Kai CHANG, Yi-Ching LIU, Yu-Ming LIN, Yih WANG, Chieh LEE
  • Publication number: 20240072128
    Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: Tsan-Chun Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240071950
    Abstract: Integrated circuit packages and methods of forming the same are discussed. In an embodiment, a device includes: a package substrate; a semiconductor device attached to the package substrate; an underfill between the semiconductor device and the package substrate; and a package stiffener attached to the package substrate, the package stiffener includes: a main body extending around the semiconductor device and the underfill in a top-down view, the main body having a first coefficient of thermal expansion; and pillars in the main body, each of the pillars extending from a top surface of the main body to a bottom surface of the main body, each of the pillars physically contacting the main body, the pillars having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than the first coefficient of thermal expansion.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Wen-Yi Lin, Kuang-Chun Lee, Chien-Chen Li, Chien-Li Kuo, Kuo-Chio Liu
  • Patent number: 11913084
    Abstract: A quenching fixture adapted to clamp at least one workpiece is provided. The quenching fixture includes a first positioning component and a second positioning component. Both of the first positioning component and the second positioning component have a positioning surface, multiple protrusions protruding from the positioning surface and a heat dissipation channel disposed between the protrusions in a staggered manner. The positioning surface of the first positioning component faces the positioning surface of the second positioning component, and the protrusions of the first positioning component overlap the protrusions of the second positioning component. The workpiece is clamped between the protrusions of the first positioning component and the protrusions of the second positioning component.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Yi-Ta Huang, Cheng-Nan Ling, Chih-Chun Liu
  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Patent number: 11908900
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Patent number: 11901323
    Abstract: A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
  • Patent number: 11894481
    Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body having a topmost surface; a first light-emitting device disposed on the carrier body and having a light-emitting surface; and a light-receiving device comprising a group III-V semiconductor material disposed on the carrier body and having a light-receiving surface. The light-emitting surface is separated from the topmost surface by first distant H1, the light-receiving surface is separated from the topmost surface by a second distance H2, and H1 is different from H2.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 6, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Yi-Chieh Lin, Shiuan-Leh Lin, Yung-Fu Chang, Shih-Chang Lee, Chia-Liang Hsu, Yi Hsiao, Wen-Luh Liao, Hong-Chi Shih, Mei-Chun Liu
  • Publication number: 20240036728
    Abstract: Methods and apparatuses for processing data are provided. In an implementation, a method comprising: obtaining, by a reduction server of a plurality of reduction servers in a distributed processing system and from a first storage area, metadata of first data to be read, wherein the first data comprises a target data block in a plurality of data blocks of second data, and wherein the second data comprises a processing result of a mapping server of a plurality of mapping servers for input data, determining a first address of the first data in a global memory based on the metadata, wherein the global memory comprises memories of the plurality of mapping servers and the plurality of reduction servers, and reading the first data from the global memory based on the first address.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 1, 2024
    Inventors: Hua XU, Xiaoming BAO, Hongwei SUN, Yihai ZHENG, Chun LIU
  • Publication number: 20240030036
    Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Application
    Filed: February 14, 2023
    Publication date: January 25, 2024
    Inventors: Sean D. Burns, Nelson M. Felix, Chi-Chun Liu, Yann A.M. Mignot, Stuart A. Sieg
  • Publication number: 20240021719
    Abstract: A semiconductor device includes a substrate and a seed layer over the substrate. The seed layer includes a first seed sublayer having a first lattice structure, wherein the first seed sublayer includes AlN, and the first seed sublayer is doped with carbon, and a second seed sublayer over the first seed layer, wherein the second seed layer has a second lattice structure different from the first lattice structure, and a thickness of the second seed sublayer ranges from about 50 nanometers (nm) to about 200 nm. The semiconductor device further includes a graded layer over the seed layer. The graded layer includes a first graded sublayer including AlGaN, having a first Al:Ga ratio; and a second graded sublayer over the first graded sublayer, wherein the second graded sublayer includes AlGaN having a second Al:Ga ratio. The semiconductor device further includes a two-dimensional electron gas (2-DEG) over the graded layer.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 18, 2024
    Inventors: Chi-Ming CHEN, Po-Chun LIU, Chung-Yi YU, Chia-Shiung TSAI, Ru-Liang LEE
  • Patent number: 11872471
    Abstract: A braking mechanism of a wheeled device is provided, including: a main body, configured to be connected to the wheeled device including at least one wheel; an adjusting member, disposed on the main body and including a rod and a first abutting member adjustably positioned on the rod; a braking member, movably disposed on the main body; and an elastic member, abutted between the first abutting member and the braking member so that the braking member is biased by the force of the elastic member toward the at least one wheel to frictionally contact the at least one wheel.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 16, 2024
    Inventors: Wen-Kuei Liu, Hsiu-Feng Chen, Chao-Hsuan Liu, Yu-Chun Liu, Yi-Shan Liu, Yu-Cheng Liu, Yan-Rui Liu
  • Publication number: 20240009742
    Abstract: A drilling guide with easily configured mounting holes for handles and insertion rods thereof includes a base, an abutting bar, two hole site structures and two insertion rods. The abutting bar slides back and forth in the second direction on the back side of the base. The hole site structures can oppositely slide in the first direction on the base, and penetrate a channel respectively, so that the drilling tool is aligned with an object on the back side of the base through the channels to process two mounting holes. The insertion rods are removably disposed in the channels. The diameter of the insertion rod changes in axial direction. The insertion rod is axially located in the channel, and the insertion rod protrudes from the bolt, and axially enters the nail hole of the handle, so as to set the distance of the mounting holes to fit the handle.
    Type: Application
    Filed: July 11, 2022
    Publication date: January 11, 2024
    Inventor: Yu-Chun LIU
  • Publication number: 20240009884
    Abstract: A mortise and tenon joint tooling guide includes a base seat, two templates, an adjusting plate and a clamping structure. The base seat has a platform and an opening through the platform. Each of the templates can be arranged on the platform at intervals in a movable form. Each of the templates is formed with a guiding edge on one side. The guiding edges face each other and are used to guide the machining tool going through the opening to process a workpiece to form a mortise or tenon. The adjusting plate is configured on the base seat, capable of moving back and forth, and is used to abut against the workpiece, and to correct the distance between the template and the surface. The clamping structure is configured on the base seat, and is used to clamp the workpiece, so as to relatively position the platform and the workpiece.
    Type: Application
    Filed: July 11, 2022
    Publication date: January 11, 2024
    Inventor: Yu-Chun LIU
  • Publication number: 20230420509
    Abstract: A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and a blocking wall. The substrate includes first and second fins separated by an insulating region. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets disposed on the second fin. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first strained layer is disposed on the first fin adjacent to the first stack of semiconductor nanosheets. The second strained layer is disposed on the second fin adjacent to the second stack of semiconductor nanosheets. The blocking wall is disposed on the insulating region and located between the first and second strained layers. The top surface of the blocking wall is higher than the top surface of the first strained layer or the second strained layer.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Chang, Jia-Chuan You, Yu-Chun Liu, Kuo-Cheng Chiang, Chih-Hao Wang