Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

Abstract: A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.

Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body having a topmost surface; a first light-emitting device disposed on the carrier body and having a light-emitting surface; and a light-receiving device comprising a group III-V semiconductor material disposed on the carrier body and having a light-receiving surface. The light-emitting surface is separated from the topmost surface by first distant H1, the light-receiving surface is separated from the topmost surface by a second distance H2, and H1 is different from H2.

Abstract: Methods and apparatuses for processing data are provided. In an implementation, a method comprising: obtaining, by a reduction server of a plurality of reduction servers in a distributed processing system and from a first storage area, metadata of first data to be read, wherein the first data comprises a target data block in a plurality of data blocks of second data, and wherein the second data comprises a processing result of a mapping server of a plurality of mapping servers for input data, determining a first address of the first data in a global memory based on the metadata, wherein the global memory comprises memories of the plurality of mapping servers and the plurality of reduction servers, and reading the first data from the global memory based on the first address.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: A semiconductor device includes a substrate and a seed layer over the substrate. The seed layer includes a first seed sublayer having a first lattice structure, wherein the first seed sublayer includes AlN, and the first seed sublayer is doped with carbon, and a second seed sublayer over the first seed layer, wherein the second seed layer has a second lattice structure different from the first lattice structure, and a thickness of the second seed sublayer ranges from about 50 nanometers (nm) to about 200 nm. The semiconductor device further includes a graded layer over the seed layer. The graded layer includes a first graded sublayer including AlGaN, having a first Al:Ga ratio; and a second graded sublayer over the first graded sublayer, wherein the second graded sublayer includes AlGaN having a second Al:Ga ratio. The semiconductor device further includes a two-dimensional electron gas (2-DEG) over the graded layer.

Abstract: A braking mechanism of a wheeled device is provided, including: a main body, configured to be connected to the wheeled device including at least one wheel; an adjusting member, disposed on the main body and including a rod and a first abutting member adjustably positioned on the rod; a braking member, movably disposed on the main body; and an elastic member, abutted between the first abutting member and the braking member so that the braking member is biased by the force of the elastic member toward the at least one wheel to frictionally contact the at least one wheel.

Abstract: A drilling guide with easily configured mounting holes for handles and insertion rods thereof includes a base, an abutting bar, two hole site structures and two insertion rods. The abutting bar slides back and forth in the second direction on the back side of the base. The hole site structures can oppositely slide in the first direction on the base, and penetrate a channel respectively, so that the drilling tool is aligned with an object on the back side of the base through the channels to process two mounting holes. The insertion rods are removably disposed in the channels. The diameter of the insertion rod changes in axial direction. The insertion rod is axially located in the channel, and the insertion rod protrudes from the bolt, and axially enters the nail hole of the handle, so as to set the distance of the mounting holes to fit the handle.

Abstract: A mortise and tenon joint tooling guide includes a base seat, two templates, an adjusting plate and a clamping structure. The base seat has a platform and an opening through the platform. Each of the templates can be arranged on the platform at intervals in a movable form. Each of the templates is formed with a guiding edge on one side. The guiding edges face each other and are used to guide the machining tool going through the opening to process a workpiece to form a mortise or tenon. The adjusting plate is configured on the base seat, capable of moving back and forth, and is used to abut against the workpiece, and to correct the distance between the template and the surface. The clamping structure is configured on the base seat, and is used to clamp the workpiece, so as to relatively position the platform and the workpiece.

Abstract: A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and a blocking wall. The substrate includes first and second fins separated by an insulating region. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets disposed on the second fin. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first strained layer is disposed on the first fin adjacent to the first stack of semiconductor nanosheets. The second strained layer is disposed on the second fin adjacent to the second stack of semiconductor nanosheets. The blocking wall is disposed on the insulating region and located between the first and second strained layers. The top surface of the blocking wall is higher than the top surface of the first strained layer or the second strained layer.

Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.

Abstract: Capacitors and interconnect structures that couple transistors to one another include parallel stacked metal lines separated by dielectric layers. When capacitors and interconnect structures are combined, each top metal capacitor plate can be coupled to the nearest upper metal line by a through-via, while each bottom metal capacitor plate can be coupled directly to the nearest lower metal line without a via. When a back end of line (BEOL) cell includes multiple capacitors, and design rules require shrinking the cell dimensions, substituting an alternative design that has fewer through-vias can facilitate compaction of the BEOL cell. Similarly, placing capacitors in close proximity so that they can share through-vias can allow even further compaction.

Abstract: A method for reconstructing a motion track applied to a terminal is provided. The method includes: obtaining a data set, the data set including positioning data obtained by positioning a target object; performing data fitting on target data in the data set to obtain a plurality of segments of first curves, the target data being positioning data obtained by performing noise filtering on the data set; and determining a motion track of the target object based on the plurality of segments of first curves. Counterpart apparatus and non-transitory computer-readable storage medium embodiments are also contemplated.

Abstract: A portable electronic device including a first body, a second body, and a hinge mechanism is provided. The second body is connected to the first body through the hinge mechanism, and the hinge mechanism has a basis axis located at the first body and a rotation axis located at a lower end of the second body. When the second body rotates with respect to the first body, the rotation axis slides along an arc shaped path with respect to the basis axis to increase or decrease a distance between the rotation axis and the basis axis and increase or decrease a distance between the lower end of the second body and a back end of the first body.

Abstract: An LED illumination device and a color temperature switching method thereof are provided. The LED illumination device includes a bridge rectifier chip, a microcontroller module, a first semiconductor switch module, a second semiconductor switch module, a first current limiting module, a second current limiting module, and a first light-emitting module and a second light-emitting module. The microcontroller module includes a microcontroller chip. The first semiconductor switch module includes a first semiconductor switch chip for receiving a first pulse width modulation signal output from the microcontroller chip. The second semiconductor switch module includes a second semiconductor switch chip for receiving a second pulse width modulation signal output from the microcontroller chip. When the AC power is supplied to the LED illumination device, the first and the second semiconductor switch modules are turned on and maintained within a predetermined turn-on percentage range without being completely turned off.

Abstract: An electronic device, including a host, a main display, an auxiliary display, and a lifting mechanism, is provided. The main display is pivoted to the host. The auxiliary display is disposed on the host. The lifting mechanism is disposed between the auxiliary display and the host. The lifting mechanism is configured to lift the auxiliary display and maintain a lifting height of the auxiliary display.

Abstract: A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The method includes depositing a dielectric layer on a substrate, forming a trench within the dielectric layer and the substrate, forming an epitaxial structure within the trench, and forming a barrier layer with first and second layer portions. The first layer portion is formed on a sidewall portion of the trench that is not covered by the epitaxial structure. The method further includes forming a capping layer on the epitaxial structure and adjacent to the barrier layer, selectively doping regions of the epitaxial structure and the capping layer, selectively forming a silicide layer on the doped regions, depositing an etch stop layer on the silicide layer, and forming conductive plugs on the silicide layer through the etch stop layer.

Abstract: A method of operating a computing system comprises defining a zoned namespace for non-volatile memory (NVM) of a memory device of the computing system, the zoned namespace including multiple NVM zones of multiple non-overlapping logical block addresses (LBAs) of the NVM, mapping persistence logging (PLOG) identifiers (IDs) to the NVM zones, a PLOG ID identifying a PLOG zone of one or more NVM zones, and performing a PLOG-specific access operation on a PLOG zone of the NVM in response to a PLOG-specific command received from a host device of the computing system.

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.