Patents by Inventor Chun Liu

Chun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11208793
    Abstract: A sanitary equipment with a water supply system, a water route system, and a hand washing table are provided. The sanitary equipment includes a machine having a machine water outlet; a movable hand washing table pivoted on the machine and located below the machine water outlet, the movable hand washing table being capable of opening or retracting with respect to the machine; and a water route system disposed in the machine and connected to the machine water outlet to discharge potable water and non-potable water from the machine water outlet.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: December 28, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Po-Chun Liu, Wen-Yi Chiu, Pin-Hsing Lee
  • Publication number: 20210397510
    Abstract: Systems, methods, and apparatus including computer-readable mediums for managing open blocks in memory systems such as NAND flash memory devices are provided. In one aspect, a memory system includes a memory and a memory controller. The memory includes multiple blocks each having a plurality of word lines. The memory controller is coupled to the memory and configured to: evaluate a read disturbance level of an open block, the open block having one or more programmed word lines and one or more blank word lines, and in response to determining that the read disturbance level of the open block is beyond a threshold level, manage each memory cell in at least one of the blank word lines to have a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines so as to reduce impact of read disturbance.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 23, 2021
    Inventors: Yi-Chun Liu, Wei Jie Chen, Ching Ting Lu, Zheng Wu
  • Publication number: 20210400805
    Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.
    Type: Application
    Filed: September 1, 2021
    Publication date: December 23, 2021
    Applicant: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Publication number: 20210398758
    Abstract: A button structure of an input device, including a circuit board, a dome element, and a trigger, is provided. The dome element is disposed on the circuit board, and is electrically conductive and elastic. The trigger is disposed at a center of the dome element, and is electrically insulative and flexible. The trigger has a conductive layer facing the circuit board. The dome element is configured to be pressed to drive the conductive layer of the trigger to abut against a trigger circuit of the circuit board to generate a trigger signal.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 23, 2021
    Applicant: Acer Incorporated
    Inventors: Yu-Shih Wang, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
  • Publication number: 20210391435
    Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu
  • Patent number: 11202357
    Abstract: A two-wire dimming lighting device includes an encoding circuit, a decoding circuit, a light source driving circuit, and an LED light emitting circuit. The encoding circuit wirelessly receives the dimming instruction, encodes an AC power according to the dimming instruction, and then outputs an encoded AC power. The decoding circuit receives the encoded AC power and then decodes the encoded AC power to obtain a light source driving instruction. The light source driving circuit receives the light source driving instruction and controls the changes of light emission of the LED light emitting circuit according to the light source driving instruction. The encoding circuit transmits the encoded AC power to the decoding circuit through a two-wire AC transmission wire.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: December 14, 2021
    Assignee: PARAGON SEMICONDUCTOR LIGHTING TECHNOLOGY CO., LTD.
    Inventors: Chia-Tin Chung, Pei-Chun Liu
  • Patent number: 11202375
    Abstract: A device that includes a substrate including a plurality of metal layers, and a plurality of dielectric layers. The device further includes a first passive component including a first terminal, a second terminal, and a first body, mounted to the substrate on one of the plurality of metal layers. The first terminal is coupled to a first ground signal and the second terminal is coupled to a second ground signal such that the first passive component is shorted.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 14, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Yu-Chun Liu, Peter Mark Davulis
  • Publication number: 20210385943
    Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Applicant: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Patent number: 11192101
    Abstract: A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chi-Chun Liu, Yann Mignot, Joshua T. Smith, Bassem M. Hamieh, Nelson Felix, Robert L. Bruce
  • Patent number: 11195995
    Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chi-Chun Liu, Yann Mignot, Ekmini Anuja De Silva, Nelson Felix, John Christopher Arnold
  • Publication number: 20210376086
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Application
    Filed: September 29, 2020
    Publication date: December 2, 2021
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20210375669
    Abstract: A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The method includes depositing a dielectric layer on a substrate, forming a trench within the dielectric layer and the substrate, forming an epitaxial structure within the trench, and forming a barrier layer with first and second layer portions. The first layer portion is formed on a sidewall portion of the trench that is not covered by the epitaxial structure. The method further includes forming a capping layer on the epitaxial structure and adjacent to the barrier layer, selectively doping regions of the epitaxial structure and the capping layer, selectively forming a silicide layer on the doped regions, depositing an etch stop layer on the silicide layer, and forming conductive plugs on the silicide layer through the etch stop layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chun LIU, Eugene I-Chun CHEN, Chun-Kai LAN
  • Publication number: 20210375672
    Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.
    Type: Application
    Filed: December 4, 2020
    Publication date: December 2, 2021
    Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Hao Chun Liu, Po-Hao Tsai, Chih-Hsien Lin, Ching-Wen Hsiao
  • Publication number: 20210373335
    Abstract: A head mounted display is provided, including a transmissive display, a first lens, a second lens, and a beam splitter coating. The transmissive display includes an active surface. The transmissive display generates a display image beam on the active surface. The first lens includes a first surface facing the active surface of the transmissive display, and a second surface opposite to the first surface. The second lens includes a third surface and a fourth surface opposite to each other. The beam splitter coating is disposed between the second surface of the first lens and the third surface of the second lens. The third surface of a second lens and the second surface of the first lens are attached to each other through the beam splitter coating, the first lens is a convex lens, and the second lens is a concave lens.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Applicant: HTC Corporation
    Inventors: Meng-Che Tsai, Kuei-Chun Liu, Ching-Chia Chou, Sheng-Le Wang
  • Publication number: 20210346148
    Abstract: An adjustable fixation system for coupling a tissue or graft to bone is disclosed including a suture construct including a first limb, a second limb and a body therebetween. The body is continuously braided with the first and second limbs and has a longitudinal passage therethrough. The first and second limbs define a braided portion including a braided core. The suture construct is configured to form at least one adjustable loop formed by passing the first limb between braids of the suture construct, along the longitudinal passage and back out between braids of the adjustable suture construct. Tension on at least one of the first or second limbs reduces a diameter of the longitudinal passage around a length of the first limb and thereby the braided core disposed along the body longitudinal passage and knotlessly locks the adjustable loop.
    Type: Application
    Filed: May 5, 2021
    Publication date: November 11, 2021
    Inventors: Ali Hosseini, Christopher David MacCready, Paul McGovern, Chun Liu, Geoffrey Ian Karasic
  • Patent number: 11171002
    Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: November 9, 2021
    Assignee: Tessera, Inc.
    Inventors: John C. Arnold, Anuja E. DeSilva, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Publication number: 20210342094
    Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 4, 2021
    Applicant: Macronix International Co., Ltd.
    Inventors: Ting-Yu Liu, Yi-Chun Liu
  • Publication number: 20210333898
    Abstract: A touch pad structure includes a touch module, a first bracket, a second bracket, and a plurality of linkage rods. The first bracket has a plurality of first pivoting portions, and the touch module is disposed on the first bracket. The second bracket has a plurality of second pivoting portions. Each of the linkage rods is pivotally connected between the first pivoting portion and the second pivoting portion, so that the touch module is moved together with the first bracket when the touch module is pressed. One portion of each of the linkage rods is pivotally rotated at the first pivoting portion, and another portion of each of the linkage rods is pivotally rotated and moved at the second pivoting portion, so that the touch module and the first bracket are moved toward a plane where the second bracket is located.
    Type: Application
    Filed: January 14, 2021
    Publication date: October 28, 2021
    Applicant: Acer Incorporated
    Inventors: Yu-Shih Wang, Wen-Chieh Tai, Cheng-Nan Ling, Chih-Chun Liu
  • Publication number: 20210335619
    Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Application
    Filed: June 7, 2021
    Publication date: October 28, 2021
    Inventors: Sean D. Burns, Nelson M. Felix, Chi-Chun Liu, Yann A.M. Mignot, Stuart A. Sieg
  • Patent number: D937992
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: December 7, 2021
    Assignee: TAIZHOU XIANGZONG FIRE SAFETY EQUIPMENT CO., LTD.
    Inventors: Jian Chun Liu, Qun Li Liu