Patents by Inventor Chun Liu

Chun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20220029087
    Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.
    Type: Application
    Filed: August 19, 2020
    Publication date: January 27, 2022
    Inventors: Yu-Chun Chen, Yen-Chun Liu, Ya-Sheng Feng, Chiu-Jung Chiu, I-Ming Tseng, Yi-An Shih, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
  • Semiconductor device and manufacturing method thereof
    Patent number: 11233120
    Abstract: The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio differences among the regrown source/drain layers are tuned to reduce strain mismatch among the semiconductor nanosheets. Alternatively, the GAA transistor may include strained channels formed using a layer stack of alternating semiconductor layers having different lattice constants.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: January 25, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En Tsai, Chia-Che Chung, Chee-Wee Liu, Fang-Liang Lu, Yu-Shiang Huang, Hung-Yu Yeh, Chien-Te Tu, Yi-Chun Liu
  • Self-priming resist for generic inorganic hardmasks
    Patent number: 11226561
    Abstract: A self-priming resist may be formed from a first random copolymer forming a resist and a polymer brush having the general formula poly(A-r-B)-C-D, wherein A is a first polymer unit, B is a second polymer unit, wherein A and B are the same or different polymer units, C is a cleavable unit, D is a grafting group and r indicates that poly(A-r-B) is a second random copolymer formed from the first and second polymer units. The first random copolymer may be the same or different from the second random polymer. The self-priming resist can create a one-step method for forming an adhesion layer and resist by using the resist/brush blend.
    Type: Grant
    Filed: August 11, 2018
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chi-Chun Liu, Indira Seshadri, Kristin Schmidt, Nelson Felix, Daniel Sanders, Jing Guo, Ekmini Anuja De Silva, Hoa Truong
  • Dry process connected energy-consuming beam column joint based on corbel
    Patent number: 11225786
    Abstract: A dry process connected energy-consuming beam column joint based on a corbel includes a prefabricated concrete corbel column, pre-buried steel plates and connecting steel plates, wherein the corbel section of the prefabricated concrete corbel column is stepped, and a notch section of a prefabricated concrete notch beam is matched with the stepped section of the corbel and is in lap joint to the stepped section; the pre-buried steel plates are separately pre-buried on the upper and lower surfaces of the corbel and the prefabricated concrete notch beam, friction plates are arranged outside the pre-buried steel plates, and slight tooth spaces are arranged on the sides, facing the pre-buried steel plates, of the friction plates; and the connecting steel plates are arranged on the left and right sides of the prefabricated concrete notch beam and the corbel lap joint section.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 18, 2022
    Assignee: Southwest Jiaotong University
    Inventors: Zhixiang Yu, Yuntao Jin, Chun Liu, Liping Guo, Liru Luo, Wenjun Gao, Hu Xu, Lei Zhao, Rui Guo
  • ELECTRONIC DEVICE
    Publication number: 20220004227
    Abstract: An electronic device, including a host, a main display, an auxiliary display, and a lifting mechanism, is provided. The main display is pivoted to the host. The auxiliary display is disposed on the host. The lifting mechanism is disposed between the auxiliary display and the host. The lifting mechanism is configured to lift the auxiliary display and maintain a lifting height of the auxiliary display.
    Type: Application
    Filed: February 22, 2021
    Publication date: January 6, 2022
    Applicant: Acer Incorporated
    Inventors: Chia-Bo Chen, Yi-Hsuan Yang, Chuan-Hua Wang, Chih-Chun Liu, Wu-Chen Lee
  • SEMICONDUCTOR PHOTO-DETECTING DEVICE
    Publication number: 20210408310
    Abstract: A photo-detecting device includes a substrate, a first semiconductor layer, a light-absorbing layer, a second semiconductor layer, a semiconductor contact layer, an insulating layer, and an electrode structure. The second semiconductor layer includes a first region and a second region. The semiconductor contact layer is on the first region. The insulating layer covers the semiconductor contact layer, the first region, and the second region. The electrode structure covers the semiconductor contact layer, the insulating layer, the first region, and the second region.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Chu-Jih Su, Chao-Shun Huang, Shiuan-Leh Lin, Shih-Chang Lee, Wen-Luh Liao, Mei-Chun Liu
  • SEMICONDUCTOR PHOTO-DETECTING DEVICE
    Publication number: 20210408311
    Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 30, 2021
    Inventors: Chu-Jih SU, Chia-Hsiang CHOU, Wei-Chih PENG, Wen-Luh LIAO, Chao-Shun HUANG, Hsuan-Le LIN, Shih-Chang LEE, Mei Chun LIU, Chen OU
  • Sanitary equipment with water supply system, water route system and sink
    Patent number: 11208793
    Abstract: A sanitary equipment with a water supply system, a water route system, and a hand washing table are provided. The sanitary equipment includes a machine having a machine water outlet; a movable hand washing table pivoted on the machine and located below the machine water outlet, the movable hand washing table being capable of opening or retracting with respect to the machine; and a water route system disposed in the machine and connected to the machine water outlet to discharge potable water and non-potable water from the machine water outlet.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: December 28, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Po-Chun Liu, Wen-Yi Chiu, Pin-Hsing Lee
  • Managing Open Blocks in Memory Systems
    Publication number: 20210397510
    Abstract: Systems, methods, and apparatus including computer-readable mediums for managing open blocks in memory systems such as NAND flash memory devices are provided. In one aspect, a memory system includes a memory and a memory controller. The memory includes multiple blocks each having a plurality of word lines. The memory controller is coupled to the memory and configured to: evaluate a read disturbance level of an open block, the open block having one or more programmed word lines and one or more blank word lines, and in response to determining that the read disturbance level of the open block is beyond a threshold level, manage each memory cell in at least one of the blank word lines to have a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines so as to reduce impact of read disturbance.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 23, 2021
    Inventors: Yi-Chun Liu, Wei Jie Chen, Ching Ting Lu, Zheng Wu
  • SUBSTRATE STRUCTURE WITH HIGH REFLECTANCE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20210400805
    Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.
    Type: Application
    Filed: September 1, 2021
    Publication date: December 23, 2021
    Applicant: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • BUTTON STRUCTURE OF INPUT DEVICE
    Publication number: 20210398758
    Abstract: A button structure of an input device, including a circuit board, a dome element, and a trigger, is provided. The dome element is disposed on the circuit board, and is electrically conductive and elastic. The trigger is disposed at a center of the dome element, and is electrically insulative and flexible. The trigger has a conductive layer facing the circuit board. The dome element is configured to be pressed to drive the conductive layer of the trigger to abut against a trigger circuit of the circuit board to generate a trigger signal.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 23, 2021
    Applicant: Acer Incorporated
    Inventors: Yu-Shih Wang, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
  • SOURCE /DRAINS IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING THEREOF
    Publication number: 20210391435
    Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu
  • Two-wire dimming lighting device
    Patent number: 11202357
    Abstract: A two-wire dimming lighting device includes an encoding circuit, a decoding circuit, a light source driving circuit, and an LED light emitting circuit. The encoding circuit wirelessly receives the dimming instruction, encodes an AC power according to the dimming instruction, and then outputs an encoded AC power. The decoding circuit receives the encoded AC power and then decodes the encoded AC power to obtain a light source driving instruction. The light source driving circuit receives the light source driving instruction and controls the changes of light emission of the LED light emitting circuit according to the light source driving instruction. The encoding circuit transmits the encoded AC power to the decoding circuit through a two-wire AC transmission wire.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: December 14, 2021
    Assignee: PARAGON SEMICONDUCTOR LIGHTING TECHNOLOGY CO., LTD.
    Inventors: Chia-Tin Chung, Pei-Chun Liu
  • Surface mount passive component shorted together
    Patent number: 11202375
    Abstract: A device that includes a substrate including a plurality of metal layers, and a plurality of dielectric layers. The device further includes a first passive component including a first terminal, a second terminal, and a first body, mounted to the substrate on one of the plurality of metal layers. The first terminal is coupled to a first ground signal and the second terminal is coupled to a second ground signal such that the first passive component is shorted.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 14, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Yu-Chun Liu, Peter Mark Davulis
  • SUBSTRATE STRUCTURE WITH HIGH REFLECTANCE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20210385943
    Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Applicant: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Method to create multilayer microfluidic chips using spin-on carbon as gap filling materials
    Patent number: 11192101
    Abstract: A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chi-Chun Liu, Yann Mignot, Joshua T. Smith, Bassem M. Hamieh, Nelson Felix, Robert L. Bruce
  • Back-end-of-line compatible processing for forming an array of pillars
    Patent number: 11195995
    Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chi-Chun Liu, Yann Mignot, Ekmini Anuja De Silva, Nelson Felix, John Christopher Arnold
  • PASSIVATION LAYER FOR EPITAXIAL SEMICONDUCTOR PROCESS
    Publication number: 20210376086
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Application
    Filed: September 29, 2020
    Publication date: December 2, 2021
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • SURFACE UNIFORMITY CONTROL IN PIXEL STRUCTURES OF IMAGE SENSORS
    Publication number: 20210375669
    Abstract: A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The method includes depositing a dielectric layer on a substrate, forming a trench within the dielectric layer and the substrate, forming an epitaxial structure within the trench, and forming a barrier layer with first and second layer portions. The first layer portion is formed on a sidewall portion of the trench that is not covered by the epitaxial structure. The method further includes forming a capping layer on the epitaxial structure and adjacent to the barrier layer, selectively doping regions of the epitaxial structure and the capping layer, selectively forming a silicide layer on the doped regions, depositing an etch stop layer on the silicide layer, and forming conductive plugs on the silicide layer through the etch stop layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chun LIU, Eugene I-Chun CHEN, Chun-Kai LAN
  • Flexible hose with hose connector
    Patent number: D937992
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: December 7, 2021
    Assignee: TAIZHOU XIANGZONG FIRE SAFETY EQUIPMENT CO., LTD.
    Inventors: Jian Chun Liu, Qun Li Liu